Presentation on theme: "D-Type Flip Flops Benchmark Companies Inc PO Box"— Presentation transcript:
1 D-Type Flip Flops Benchmark Companies Inc PO Box 473768 Aurora CO 80047
2 Lecture Overview D Flip-Flops Asynchronous Input Sample Flip-Flop Applications
3 Gated D-Type Latch The D-Latch is an expanded version of an RS Flip Flop. The symbol shown is used to represent this type of flip-flop.
4 Gated D-Type Latch It is also known as transparent latch, data latch, or simply a gated latch
5 Gated D-Type Latch It has a data input and an enable signal (sometimes named clock or control).
6 D-Type Flip-Flops The D flip-flop can be interpreted as a primitive delay line or zero-order hold, since the data is posted at the output one clock cycle after it arrives at the input
7 D Flip-Flop The Data Table below illustrates the output Q(n+1) with respect to the Data (D) clocked (CLK) into the latch.D QQCLKQ n+11D
8 D Flip-Flop As illustrated below the clock pulse into the Flip Flop (FF) will synchronize the output.CLKQ n+11DD QQCLKDQ
9 Application of D Flip-Flops Data StorageCounters & State Machine DesignsLogic SynchronizingDivide By Circuits
10 Logic Synchronizing Synchronizing data is done by clocking all D-Type FF with the same clock. This puts data on A,B and C at the same time.
11 Divide By Circuit using a D Flip-Flop The D-Type FF can be configured to divide the pulse in half by configuring the circuit below.SIG_INSIG_OUT
12 Types of D Flip-FlopsD QQPositive Edge TriggeredNegative Edge TriggeredD QQThe trigger happens during the designed trigger edge.
13 Types of D Flip-FlopsD QQPositive Level TriggeredD QQNegative Level TriggeredThe trigger happens during the designed trigger level
14 D Flip-Flop w/ Preset & Clear D Q Q Types of D Flip-FlopsAsynchronous InputsD Flip-Flop w/ Preset & ClearD QQP-SETCLRQ n+11 (preset)0 (clear)? (illegal)1CLKXDCLRP-SETThe FF can be designed with Preset (P-SET) or clear (CLR)