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D-Type Flip Flops Benchmark Companies Inc PO Box 473768 Aurora CO 80047
Lecture Overview D Flip-Flops Asynchronous Input Sample Flip-Flop Applications
Gated D-Type Latch The D-Latch is an expanded version of an RS Flip Flop. The symbol shown is used to represent this type of flip- flop.
Gated D-Type Latch It is also known as transparent latch, data latch, or simply a gated latch
Gated D-Type Latch It has a data input and an enable signal (sometimes named clock or control).
D-Type Flip-Flops The D flip-flop can be interpreted as a primitive delay line or zero-order hold, since the data is posted at the output one clock cycle after it arrives at the input
D Flip-Flop The Data Table below illustrates the output Q(n+1) with respect to the Data (D) clocked (CLK) into the latch. CLK Q n+1 0 1 D01D01 D Q Q
D Flip-Flop As illustrated below the clock pulse into the Flip Flop (FF) will synchronize the output. CLK Q n+1 0 1 D01D01 D Q Q CLK D Q
Application of D Flip-Flops Data Storage Counters & State Machine Designs Logic Synchronizing Divide By Circuits
Logic Synchronizing Synchronizing data is done by clocking all D-Type FF with the same clock. This puts data on A,B and C at the same time.
Divide By Circuit using a D Flip-Flop The D-Type FF can be configured to divide the pulse in half by configuring the circuit below. SIG_IN SIG_OUT
Types of D Flip-Flops D Q Q Positive Edge TriggeredNegative Edge Triggered D Q Q The trigger happens during the designed trigger edge.
D Q Q Negative Level Triggered D Q Q Positive Level Triggered Types of D Flip-Flops The trigger happens during the designed trigger level
D Flip-Flop w/ Preset & Clear D Q Q P-SET CLR Types of D Flip-Flops Asynchronous Inputs Q n+1 1 (preset) 0 (clear) ? (illegal) 0 1 CLK X DXXX01DXXX01 CLR 1 0 1 P-SET 0 1 0 1 The FF can be designed with Preset (P-SET) or clear (CLR)