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Paul Scherrer Institute
Stefan Ritt Plans for the DRS5 Switched Capacitor Array Clermont Ferrand, January 28th, 2011
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Agenda DRS4 Chip Evaluation Board
DRS4 chip has been developed at PSI and has been shown at this Workshop in 2009/2010 No new chip developments since 2008, but WaveDREAM board developed at PSI CAEN VME board ToF-PET Application under investigation New ideas for DRS5 to be designed in 2011 Increased bandwidth Zero dead time DRS4 Chip Evaluation Board Clermont Ferrand, January 28th, 2011
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DRS4 Chip Clermont Ferrand, January 28th, 2011
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DRS4 Fabricated in 0.25 mm 1P5M MMC process (UMC), 5 x 5 mm2, radiation hard 8+1 ch. each 1024 bins, 4 ch. 2048, …, 1 ch. 8192 Passive differential inputs/outputs Sampling speed 700 MHz … 5 GHz On-chip PLL stabilization Readout speed 30 MHz, multiplexed or in parallel Clermont Ferrand, January 28th, 2011
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Bandwidth Evaluation board QFP package THS4508 Measurement
Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) QFP package final bus width THS4508 850 MHz (-3dB) 800 MHz (-3dB) Measurement Clermont Ferrand, January 28th, 2011
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ROI readout mode e.g. 100 samples @ 33 MHz 3 us dead time
delayed trigger stop normal trigger stop after latency Trigger stop Delay 33 MHz e.g MHz 3 us dead time 300,000 events / sec. readout shift register Patent pending! Clermont Ferrand, January 28th, 2011
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Daisy-chaining of channels
Domino Wave Domino Wave clock clock 1 enable input Channel 0 enable input Channel 0 enable input Channel 1 1 enable input Channel 1 1 Channel 2 Channel 2 Channel 3 1 Channel 3 1 Channel 4 Channel 4 Channel 5 1 Channel 5 1 Channel 6 Channel 6 Channel 7 1 Channel 7 DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth Clermont Ferrand, January 28th, 2011
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Simultaneous Write/Read
FPGA Channel 0 readout 1 Channel 0 Channel 0 Channel 1 Channel 1 1 Channel 1 8-fold analog multi-event buffer Channel 2 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Expected crosstalk ~few mV Clermont Ferrand, January 28th, 2011
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DRS4 around the world Shipped (-Jan 2011): 2200 Chips
120 Evaluation Boards Clermont Ferrand, January 28th, 2011
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MEG Status MEG experiment @ PSI searches for meg decay
After ~10 years of chip design, DAQ setup, firmware programming, MEG runs with 3000 channels as designed 40 ps timing resolutions between all channels, running at 1.6 GS/s “Double buffer” readout mode increases life time to 99.7 % at 10 Hz event rate (3 MB/event) Took 400 TB in 2010 Clermont Ferrand, January 28th, 2011
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Trigger and DAQ on same board
SCA can only sample a limited (1024-bin window) many application require a wider window, trigger capability would require continuous digitization Using a multiplexer in DRS4, input signals can simultaneously digitized at 120 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (5 GSPS) though same 8-channel FADCs DRS4 global trigger bus trigger FPGA MUX DRS FADC 12 bit 65 MHz analog front end LVDS SRAM Clermont Ferrand, January 28th, 2011
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“Slow” waveform and “Fast” window
Triggered DRS Waveform 1 GSPS (1 ns bins) up to 5 GSPS Window only limited by RAM Continuous Waveform 120 MSPS (8 ns bins) Clermont Ferrand, January 28th, 2011
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(H. Friederich, PSI & ETH)
WaveDREAM Board Empty VME slot costs ~1kE USB is limited in speed (2.0) and scaling WaveDREAM board developed at PSI with GBit Ethernet New board planned VGA at input (10 mV – 10 V inputs) 16 Channels on Eurocard, MMCX connectors Standalone or cascadable Serial bus for data, trigger & synchronization Plug & Play Firmware: TDC, CFD, ADC, Scaler, MCA, … WaveDREAM (H. Friederich, PSI & ETH) New Board 16 chn + serial bus Eth DRS4 ADC Serial links and trigger VGA GBit FPGA Pre- Ethernet amp DRS4 ADC RAM Pre- amp Clermont Ferrand, January 28th, 2011
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Digital Oscilloscope Front-end
Clermont Ferrand, January 28th, 2011
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Plug & Play Firmware Pre-designed modules for CFD, TDC, peak sensing ADC, … Modules can be configured by user and downloaded over Ethernet CFD TDC FIFO Chip Readout SCALER Interface FIFO FIFO ADC FIFO Data bus Parameter bus Clermont Ferrand, January 28th, 2011
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CAEN V1742 Board 32+2 Channels 12 bit 5 GS/s Digitizer
VME64X + optical link New board design by CAEN in line with their ADC boards Firmware support by CAEN “Early adopter phase” started 2010, official board announcement March 2011 Desktop version planned Clermont Ferrand, January 28th, 2011
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Digital Pulse Processing (DPP)
C. Tintori (CAEN) V. Jordanov et al., NIM A353, 261 (1994) Clermont Ferrand, January 28th, 2011
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g-n Pulse-shape Discrimination
C. Tintori (CAEN) Clermont Ferrand, January 28th, 2011
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DPP PSI Clermont Ferrand, January 28th, 2011
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Time-of-Flight PET Conventional electronics: CFD – TDC: 500 ps RMS
TOF needs: ps >1 MHz rate C. Levin, Stanford University Clermont Ferrand, January 28th, 2011
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ToF-PET Project “Ping-Pong Scheme” 20 samples (10 ns @ 2 GS/s)
Started fall 2010 after NSS/MIC in Knoxville (Siemens PET R&D home) New project started to replace current PET electronics with DRS4 (5) PCB ready summer 2011, firmware by Univ. Tübingen Simulations show that SCA technique can achieve 100 ps easily FPGA “Ping-Pong Scheme” 1 Channel 0 Channel 0 Channel 1 Channel 1 ROI Channel 2 20 samples (10 2 GS/s) * 30 ns / sample = 600 ns + 40 ns overhead = 640 ns 1 MHz rate Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Clermont Ferrand, January 28th, 2011
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DRS5 Chip Clermont Ferrand, January 28th, 2011
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Plans for DRS5 mSR CTA Increase analog bandwidth ~5 GHz
Smaller input capacitance Increase sampling speed ~10 GS/s Switch to 180 nm technology Deeper sampling depth 8 x 4096 / chip Minimize readout time (“dead time free”) for muSR & ToF-PET (minor) reduction in analog readout speed (30 ns 20 ns) Implement FIFO technology J. Milnes, J. Howoth, Photek mSR ~MHz event rate CTA Clermont Ferrand, January 28th, 2011
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Why 180nm ? 250 nm process dies out: 1 MPW run / year (UMC) Pro smaller feature size: Faster sampling speed Faster readout (?) More sampling cells / area (but: routing/capacitor limitation!) Con: Smaller VDD makes analog design difficult, with 1.2V it is almost impossible to obtain a 1V linear range Price: 130 nm 3 x more expensive Compromise: 180 nm Clermont Ferrand, January 28th, 2011
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How to combine best of both worlds? Next Generation SCA
Short sampling depth Deep sampling depth Low parasitic input capacitance High bandwidth Large area low resistance bus, low resistance analog switches high bandwidth Digitize long waveforms Accommodate long trigger delay Faster sampling speed for a given trigger latency How to combine best of both worlds? Clermont Ferrand, January 28th, 2011
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Cascaded Switched Capacitor Arrays
input shift register 32 fast sampling cells (10 GSPS/180nm CMOS) 100 ps sample time, 3.1 ns hold time Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) Shift register gets clocked by inverter chain from fast sampling stage fast sampling stage secondary sampling stage Clermont Ferrand, January 28th, 2011
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Typical Waveform Only short segments of waveform need high speed readout Clermont Ferrand, January 28th, 2011
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Dead-time free acquisition
Self-trigger writing of short 32-bin segments Simultaneous reading of segments Quasi dead time-free Data driven readout Ext. ADC runs continuously ASIC tells FPGA when there is new data Coarse timing from 300 MHz counter Fine timing by waveform digitizing and analysis in FPGA 20 * 20 ns = 0.4 ms readout time 2 MHz sustained event rate Attractive replacement for CFD+TDC Clermont Ferrand, January 28th, 2011
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Conclusions DRS4 chip successfully used in many areas, true potential of SCA technology is just now discovered Planned DRS5 chip will increase BW and decrease readout dead time SCA technology should be able to replace most traditional electronics in particle detection Clermont Ferrand, January 28th, 2011
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