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GTS, Optical Link and TRACE Front End Electronics Andrea Triossi INFN - LNL PROMETEO workshop November 17-18 2011, Valencia.

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Presentation on theme: "GTS, Optical Link and TRACE Front End Electronics Andrea Triossi INFN - LNL PROMETEO workshop November 17-18 2011, Valencia."— Presentation transcript:

1 GTS, Optical Link and TRACE Front End Electronics Andrea Triossi INFN - LNL PROMETEO workshop November , Valencia

2 Outlines FEE options Reduced output Sparse readout RO and Trigger on FPGA Expected Activities FEE options Reduced output Sparse readout RO and Trigger on FPGA Expected Activities TRACE Global Trigger and Synchronization Firmware Optical Gigabit Link (LINCO) Expected Activities Global Trigger and Synchronization Firmware Optical Gigabit Link (LINCO) Expected Activities NEDA

3 GTS: Functionalities Trigger Request Local Tag Generator Local Tag Generator MGT TX RX Trigger Match Trigger Match MEM Valid / Reject Val/Rej Tag Uplink Common clock Global clock counter Global event counter Trigger requests Error reports Trigger controls: Throttling of the L1 validation signal Fast commands (fast reset, initialization, etc.) Fast monitoring feedback from the crystals Calibration and test trigger sequence commands Monitor of dead time

4 GTS: Current Limits Serves just one trigger request Interface for 16 Handles just one ID request 16 ID per GTS core Single communication interface Split into two? one towards V6 and one inside V5

5 GTS Interfaces Trigger Requests GTS Services PPC running Hardware implemented ? Linux VxWorks 22 lines (request, validation/rejection) + 16 due to requester ID (concurrent trigger requests) = 38 lines between V5 and V6

6 Adapter to translate PCI Express signals to/from the optical physical layer suitable for legacy bus standards (PCI, cPCI, VME…) What is LINCO? local bus remote bus Already adopted by several experiments: AGATA (moving from V1 to V2) CERN (since 2005 in harsh environmental conditions) ICARUS WARP Already adopted by several experiments: AGATA (moving from V1 to V2) CERN (since 2005 in harsh environmental conditions) ICARUS LNGS

7 LINCO Flavors 1x4 PCIEx / 2x2 PCIEx / 4x1 PCIEx Motherboard/Oscillator REF CLK x4 PCIEx bus Clock issues Spread Spectrum Clock Clock out of spec Clock issues Spread Spectrum Clock Clock out of spec PCIEx Switch GEN2 20 Gb/s aggregate x1 PCIEx PCI 1 REF CLK bus x1 PCIEx 1 REF CLK bus

8 LINCO V2

9 RAM PCI-Ex DMA Transfer DMA engine continuously write on PC RAM holding the processor bus. If we want to run concurrently online trigger algorithms or even analysis programs that access the main memory, the DMA transfer will be stopped DMA engine continuously write on PC RAM holding the processor bus. If we want to run concurrently online trigger algorithms or even analysis programs that access the main memory, the DMA transfer will be stopped CPU Root Complex PCI-Ex Endpoint PCI-Ex Endpoint PCI-Ex Endpoint PCI-Ex Endpoint PCI-Ex Endpoint PCI-Ex Endpoint PCI-Ex Endpoint PCI-Ex Endpoint PCI-Ex Endpoint PCI-Ex Endpoint The higher the throughput the bigger the buffering

10 Expected Activities x2 (x4) PCI Express core deployment Communication test LINCO-Numexo carrier Check compatibility issues between LINCO and PC farm x2 (x4) PCI Express core deployment Communication test LINCO-Numexo carrier Check compatibility issues between LINCO and PC farm LINCO New Firmware Test bench on a small tree (GTS mezzanine?) Test on a Numexo carrier New Firmware Test bench on a small tree (GTS mezzanine?) Test on a Numexo carrier Global Trigger and Synchronization

11 TRACE FEE Requirements CMOS 180 nm Low consumption (1-10 mW) Fast switching High integration CMOS 180 nm Low consumption (1-10 mW) Fast switching High integration Spherical chamber Ø 26cm 10K channels PA inside the chamber Spherical chamber Ø 26cm 10K channels PA inside the chamber Integrated PA Analog Memory for multiplexing TRACE ASIC Technology

12 TRACE FEE Requirements Rising time: ns Bandwidth: 0.35/20 ns = 17.5 MHz Sampling rate: 200 MHz Rising time 200 ns, 200 MHz sampling rate: 40 samples (2B each, 12bit ENOB) 128 ch per ASIC Rate/ch 100 Hz Throughput: 1MB/s per ASIC ( ~ 80) Rising time: ns Bandwidth: 0.35/20 ns = 17.5 MHz Sampling rate: 200 MHz Rising time 200 ns, 200 MHz sampling rate: 40 samples (2B each, 12bit ENOB) 128 ch per ASIC Rate/ch 100 Hz Throughput: 1MB/s per ASIC ( ~ 80) Digitizer out of the chamber PA 2 mW/ch 200 mW/ASIC 20 W/array ( ~ the same from the analog memory) Digitizer out of the chamber PA 2 mW/ch 200 mW/ASIC 20 W/array ( ~ the same from the analog memory) Consumption Throughput

13 PSA Feasibility Transient signal: 1/10 net charge (from simulation) Worst case: 5 MeV Alpha 50 mV Gain: 10 mV/MeV (which Ion set the gain? Li?) Bandwidth: 100MHz ENC 10e rms Dynamics: 150 MeV on 1.5 V Transient signal: 1/10 net charge (from simulation) Worst case: 5 MeV Alpha 50 mV Gain: 10 mV/MeV (which Ion set the gain? Li?) Bandwidth: 100MHz ENC 10e rms Dynamics: 150 MeV on 1.5 V Pre Amplifier

14 Q AmpShaper 128x128 Memory cells Input channels..... M U X 200 MHz Reduced Output..... Trigger Comp A B Q AmpShaper Input channels..... M U X 200 MHz Sparse Readout..... Encoder Comp Lookup Table Controller 128x128 Memory cells

15 V/I Amp Memory cells 128x A D C 200 MHz Trigger C Input channels F P G A High speed Serial link

16 FPGA as ADC FPGA D A C V/I AMP TDC T1T1 V1V1 T2T2 V2V2 T3T3 V3V3 T4T4 V4V4 From PA directly to FPGA differential inputs External DAC used to produce a V REF linear ramp TDCs measure time differences further converted to voltage From PA directly to FPGA differential inputs External DAC used to produce a V REF linear ramp TDCs measure time differences further converted to voltage Highest integration?

17 Dead Time MUX switching time: typ. ~ 50 ns Sampling Rate 200 MS/s per ch Samples: 40 signal + 20 baseline Memory depth: 128 samples Dead time per ch: 50 ns + 128x5 ns = 640 ns Dead time per ASIC: 128x350 ns 80 µs 80 µs ~ 12 KHz (Elastic Scattering) Simultaneous Read/Write ? ROI Read out (60 samples) ? MUX switching time: typ. ~ 50 ns Sampling Rate 200 MS/s per ch Samples: 40 signal + 20 baseline Memory depth: 128 samples Dead time per ch: 50 ns + 128x5 ns = 640 ns Dead time per ASIC: 128x350 ns 80 µs 80 µs ~ 12 KHz (Elastic Scattering) Simultaneous Read/Write ? ROI Read out (60 samples) ? Solution A

18 Read Out RO Board Multi channel ADC Preprocessing on FPGA Out of the chamber Synchronization and trigger (GTS) Multi channel ADC Preprocessing on FPGA Out of the chamber Synchronization and trigger (GTS) ADC Linear Range: 1.5 V Resolution: 10 mV Levels: 1.5 V / 10 mV = 150 Induced signals x bit ENOB Linear Range: 1.5 V Resolution: 10 mV Levels: 1.5 V / 10 mV = 150 Induced signals x bit ENOB

19 Prototype channel Analog memory (DRS4): 5 GS/s, 1024 cells, 9 ch (4 in the EVB) ADC (AD9245): 14 bit, 80 MS/s FPGA Xilinx Spartan3 Microcontroller (CY2C68013A ) with USB connection Analog memory (DRS4): 5 GS/s, 1024 cells, 9 ch (4 in the EVB) ADC (AD9245): 14 bit, 80 MS/s FPGA Xilinx Spartan3 Microcontroller (CY2C68013A ) with USB connection S. Ritt (PSI)

20 Conclusions PA ASIC development Analog memory prototype channel TDC feasibility study Global Trigger and DAQ: Compatibility Issues PA ASIC development Analog memory prototype channel TDC feasibility study Global Trigger and DAQ: Compatibility Issues TRACE Development of a New GTS Firmware Test on NUMEXO carrier Compatibility among PC-LINCO-NUMEXO Development of a New GTS Firmware Test on NUMEXO carrier Compatibility among PC-LINCO-NUMEXO NEDA


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