Secrets of the DCM: Part 1

Secrets of the DCM: Part 1
Steve Knapp General Products Division NOTICE: This is an early draft of this presentation. Please visit the Xilinx Sales Partner Web (SPW) for the latest version. スティーブ・ナップ © 2004 by Xilinx, Inc. All rights reserved. (v1.2, 11-OCT-2004)

Workshop Objectives By the end of this class, you will …
Understand the function and application of Digital Clock Managers (DCMs) Unlock a few mysteries on how DCMs operate More mysteries revealed in Part II Become a Clock Wizard and easily configure a DCM Have a few new approaches to teach customers on DCMs Legitimately say “DCMs Don’t Confuse Me”

Up the Learning Curve e s i t r e p x E Real-World Experience Part II
This class assumes that you have at least a passing familiarity with the Digital Clock Managers (DCMs) within Xilinx FPGAs. This is Part 1 of a two part class. Part 1 is designed to introduce you to basic DCM concepts and capabilities. If you’re already an advanced DCM user, I think that you’ll learn a few new techniques that you can use to teach customers and other FAEs. Part 2 extends the concepts of Part 1 and covers a few advanced areas. After attending both sessions, you should have a good work knowledge of the DCM. However, only real-world design experience will make you an expert. What’s a DCM? Time

DCMs Everywhere! In this presentation, the Spartan-3 DCM demonstrates basic principals and concepts The Spartan-3 DCM is similar to Virtex-II and Virtex-II Pro The DLL in the DCM is similar to the DLL in Virtex/E and Spartan-II/E Virtex-4 DCM also employees similar concepts And now a message from our sponsors … Spartan-3 DCMs are used in this class to demonstrate various concepts. The Spartan-3 DCM is nearly identical to that found on Virtex-II and Virtex-II Pro FPGAs, minus a few issues. The Delay Locked Loop (DLL) within each DCM is similar to the DLL found in Virtex, Virtex-E, Spartan-II, and Spartan-IIE FPGAs. Virtex-4 employees all the latest generation capabilities. However, the concepts described in this class also apply to Virtex-II.

DCMs: The Clock Problem Solver
Eliminate clock skew—improved performance! Multiply or divide an incoming clock or create a completely new clock frequency Phase shift a clock Condition a clock input to create 50% duty cycle Any or all of the above, simultaneously! QUESTION TO THE CLASS: What are a few of the clocking problems that you face in system design? PROMPTS: Ever wish that you had faster clock-to-output time? How do you obtain that? Ever wish that you could create another clock frequency? DCMs have a variety of system applications. DCMs help eliminate clock skew either within the FPGA or within the system, improving overall performance. Now some FAEs think that DCMs are there to help generate customer calls. One key message: Not every application requires a DCM. If you don’t need it, don’t use it. Unless required, DCMs are just a needless complexity.  Don’t need it? Then don’t use it!

DCM, Where Are You? XC3S50 only Located at top and bottom of block RAM/multiplier column(s) Four DCMs in each Spartan-3, except XC3S50, which has two DCM DCMs have direct connections to global buffers along the same edge Each DCM has a unique location string Watch PAR placement! Global buffer multiplexers DCM_X1Y1 DCM_X1Y0 DCM_X0Y0 DCM_X0Y1 Block RAM Column Embedded Multiplier Column Global buffer multiplexers

Delay-Locked Loop (DLL)
DCM Block Diagram Digital Frequency Synthesizer Phase Shifter (PS) Input Stage Output Stage Delay Taps Status Logic Delay-Locked Loop (DLL) DCM CLK0 CLKIN CLK90 CLK180 CLK270 Up to all nine clock outputs available simultaneously CLKFB CLK2X CLK2X180 CLKDV Any four of nine clock outputs optionally connect to global buffers along same edge CLKFX CLKFX180 PSEN PSINCDEC PSDONE PSCLK STATUS[7:0] RST LOCKED

Lesson One Avoid being skewed!

The Ideal World FPGA A B C Other Device on Board SKEW

In the Real World, You’re Skewed
FPGA B Other C A D b Device on Board D c A D b D c Two different timing relationships!

No Skew, No Problem Symbol -4 TIOCKP 1.72 ns Q CLK CLK Q
Flip-flop Delay Symbol -4 TIOCKP 1.72 ns

Skew: The Time Thief Symbol -4 TIOCKP 1.72 ns TICKOF 4.56 ns Q CLK CLK
Flip-flop Q Input Buffer Clock Distribution

Quick Review: What We Want
FPGA A B C Other Device on Board

How Do We Get There? What if we provide advance clocks? Other
B Other A C Device on Board What if we provide advance clocks?

The Answer? Clairvoyant Logic, Of Course!
B -Db + Db = NO SKEW! Other D b c A C Device on Board A D b B D c C

Houston, We Have a Problem
First Rule of Time Travel: You can’t go backwards! Clairvoyant logic does not exist (well, at least not yet) Now what!?!

Forward Thinking Other Device on Board B A C Clock Period (T) A
Delay=T - Db B b D c Delay=T- Dc C

? You Don’t! The Tough Questions How do you specify the clock period?
How do you determine the delays for Db and Dc? How do you voltage- and temperature-compensate the design? You Don’t! ?

Classroom Experiments
Everyone please take out your Delay-Lock Loop (DLL) simulators LAB 1: Feedback, frequency and phase locking LAB 2: Stable, monotonic clock

The Magical Delay-Locked Loop (DLL)
ADJUST Too Early Clock Feedback Each of the 256 taps is between 30 to 60 ps Delay Line Clock Delay matched Clock and Feedback path lengths Phase Detector Feedback

The Magical Delay-Locked Loop (DLL)
Perfect! Clock LOCKED Feedback Delay Line Clock Phase Detector Feedback Delay tap settings updated periodically for temperature/voltage compensation Update rate controlled by an internal attribute called FACTORY_JF

Resulting Timing Symbol Description -4 TIOCKP Output flip-flop clock-to-output 1.72 ns TICKOF Pin-to-pin clock-to-output delay, no DCM 4.56 ns TICKOFDCM Pin-to-pin clock-to-output delay, with DCM deskew 1.52 ns ~ 3 ns eliminated from clock distribution delay when using internal feedback! Output delay nearly completely eliminated when using external feedback

Locking The DLL requires a stable monotonic clock input
Stable clock frequency Minimal jitter The DCM LOCKED output indicates when the DCM has acquired and locked to the incoming clock Application should ignore the DCM clock outputs until LOCKED asserted No clock edges can be missing during the locking process If clock is not yet stable, hold the DCM in reset External enabled oscillators External frequency scaling Cascaded DCMs

Locking Process

LOCKED and STATUS Bits LOCKED (Output clocks good)
The DCM clock outputs are not valid until LOCKED=1 If LOCKED  0, reset the DCM (hit delay tap limits) It is possible for LOCKED=1 but the output clocks are invalid STATUS bits provide additional detail STATUS[1] – CLKIN Stopped STATUS[1]=1 if CLKIN stops toggling, reset the DCM STATUS[2] – CLKFX, CLKFX180 Stopped STATUS[2]=1 if CLKFX or CLKFX180 outputs stop, and these outputs are used in the design, reset the DCM

Feedback from a Reliable Source
DLL requires feedback from one of two DCM outputs CLK0 (1X feedback) CLK2X (2X feedback) CLK2X not presently available on all devices Presently supported only on XC3S50 and XC3S1000 Coming to the remainder of the family in 2005 Not supported in Virtex-II Pro

DCMs Integrate into FPGA Clock Path
IBUFG BUFG PAD CLKIN CLKFB CLKx DCM IBUFG BUFG PAD

Internal Feedback IBUFG BUFG DCM (or BUFGMUX, or BUFGCE) Clock to I O
CLKIN CLK0 internal (or CLK2X) FPGA logic (alternate clock inputs DCM possible, but not fully skew adjusted) CLKFB LOCKED (Internal Feedback)

External Feedback Delay matched Clock and Feedback path lengths FPGA
Other FPGA Circuit-board trace delay, additional Device(s) IBUFG OBUF clock buffers, etc. on Board I O I O CLKIN CLK0 CLK (or CLK2X) IBUFG OBUF DCM I O I O CLKFB LOCKED ENABLE SRL16 D Q RESET WCLK A[3:0] INIT=000F (External Feedback Trace) Delay matched Clock and Feedback path lengths

Clock Wizard Makes it Easy!

Lesson Two Wizard School

DCM Rules and Lots of Them
The DLL outputs operate up to 280 MHz unless you use phase shifting, then the maximum frequency is 165 MHz The DFS accepts input clock frequencies down to 1 MHz if you are not using the Delay-Locked Loop (DLL) The CLKDV output can only divide the incoming clock by certain values The variable phase shifter uses the PSEN, PSINCDEC, PSCLK, PSDONE, and STATUS bits The DLL requires that the CLKFB input be connected. The DFS does not require feedback Any four of the nine possible DCM outputs can connect to global clock buffers The CLK90 and CLK270 outputs are only available when the DLL is in low-frequency mode The output jitter on the CLKFX and CLKFX180 output depends on the DFS Multiply and Divide settings The amount of phase shift may be limited due to the incoming clock frequency The frequencies supported by the DFS may be limited by the DLL if used within the same DCM The minimum DLL output frequency must be 24 MHz or greater The DLL feedback must come from either CLK0 or CLK2X. The CLK2X feedback does not work for all devices

DCM Rule #1 All DCMs in a design must be instantiated
CLKIN CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 STATUS[7:0] LOCKED PSDONE CLKFB RST PSEN PSINCDEC PSCLK DCM DSSEN All DCMs in a design must be instantiated Language Templates available in ISE Clock Wizard makes it easy

Schematic of DCM Example
IBUFG BUFG CLKIN CLK0 33 MHz 33 MHz CLKFB CLK90 CLK_FEEDBACK = 1X CLK180 CLKDV_DIVIDE = 10 CLKFX_MULTIPLY = 29 CLK270 CLKFX_DIVIDE = 11 CLK2X CLKOUT_PHASE_SHIFT = VARIABLE DFS_FREQUENCY_MODE = LOW CLK2X180 DLL_FREQUENCY_MODE = LOW 3.3 MHz PHASE_SHIFT = 23 CLKDV CLKFX 87 MHz CLKFX180 BUFG RST PSEN STATUS PSINCDEC LOCKED PSCLK PSDONE

ISE 6.3i Clock Wizard Greatly simplifies using a DCM!
Graphically configure a Digital Clock Manager (DCM) Vendor-specific VHDL or Verilog VHDL or Verilog instatiation template Xilinx Architecture Wizard (XAW) settings file User constraints file (UCF) Greatly simplifies using a DCM!

Two Methods to Invoke Clock Wizard
From Window Start menu Start  Xilinx ISE 6  Accessories  Architecture Wizard From within Project Navigator Project  New Source

Project Navigator Method

Selecting the Right Wizard

General Setup

Assigning Global Buffers
BUFG Global Buffer I0 O BUFGCE Enabled Buffer I0 O CE BUFGMUX I0 Clock Mux O I1 S Lowskewline I0 Local Routing I0

Frequency Synthesizer
(back on General Setup)

Voila!

Instantiation Template
VHDL Example Available for both VHDL and Verilog

Lesson Three Jitter

What is Jitter? Uncertainty on exact timing of a clock edge
Ideal Clock Measured clock period N u m b e r o f s a p l Peak-to-peak Period Jitter Uncertainty on exact timing of a clock edge Affected by power noise, decoupling, SSOs, internal switching, etc. Period (peak-to-peak) jitter specification is most quoted Specified as either absolute (300 ps) or deviation (± 150 ps)

Clock Jitter Specifications
Period (peak-to-peak) jitter Cycle-to-cycle jitter Unit Interval (UI) T T 1 =T +100 ps T 2 =T 1 -150 ps Example UI=0.10 means that period jitter is 10% of the total bit period Peak-to-peak Period Jitter Bit Period Peak-to-peak period jitter, represented as fraction of Unit Interval Unit Interval (UI)

Jitter Effects on Cycle Timing
Single Data Rate (SDR) Earliest Arrival Available Period Half Period Jitter Clock Period Bit Period

Jitter Effects on Cycle Timing
Double Data Rate (DDR) Earliest Arrival Consider both clock edges in DDR applications Available Period Available Period Jitter Bit Period No duty-cycle distortion effects considered Clock Period

Jitter Effects on Flip-Flop Timing
Early Clock Edge Late Clock Edge Half Period Jitter Half Period Jitter Increases input set-up time Reduces minimum clock-to-output time Increases hold time Increases maximum clock-to-output time

Minimizing Clock Jitter
Switching noise causes jitter Proper power, PCB design, and decoupling XAPP623: Power System Distribution Guidelines PCB Checklist % CLB switching contributes noise Obey SSO recommendations (in Spartan-3 data sheet) VCCAUX is voltage source for DCMs GND pins for logic and DCMs are common Jitter on input clock Garbage in, garbage out Take care of your clocks and your clocks will take care of you

GOVERNMENT HEALTH WARNING:
FAILING TO APPLY XAPP623 COULD BE HAZARDOUS TO YOUR DCM DESIGN AND YOUR MENTAL HEALTH

XAPP462: The DCM Reference
A comprehensive 68-page “tree killer” Updated for ISE 6.3i and latest Spartan-3 DCM knowledge

Second Verse, Same as the First*
If you enjoyed this session, please also attend … Secrets of the DCM Part II * Only a little bit louder and a whole lot worse

Questions?

Please Fill Out and Return the Feedback Forms!
Forms are in the back of your FAE conference book Please return at back of the room Secrets of the DCM: Part 1 Steve Knapp ü Thank You! ü ü

Jump Point Overview Lesson 1: Avoid Being Skewed
Lesson 2: Clock Wizard School Lesson 3: Clock Jitter Session Evaluation Forms Return to last slide viewed

Secrets of the DCM: Part 1

Similar presentations

Presentation on theme: "Secrets of the DCM: Part 1"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

Secrets of the DCM: Part 1

Similar presentations

Presentation on theme: "Secrets of the DCM: Part 1"— Presentation transcript:

Similar presentations

About project

Feedback