1. Performed by: Nir Malka, Lior Rom Instructor: Mike Sumzik המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט ( חלק א ’/ סופי ) Subject: Project name סמסטר ( חורף / קיץ ) שנה 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Design a high speed analog to digital daughter board which interfaces to Altera DE3. Designing a new daughter board, which will interface to Altera DE3, and will be able to perform DAC and ADC sampling, at HS frequencies. Preparing a manufacturing file, containing Orcad schematics, and main VHDL blocks.

3. System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Sample Real Time Digital Processing (DE3) Reconstruction Analog Input Analog Output

4. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware 4 DC voltage supply: –Main DC power source from external DC supplier of 8.5V, into voltage regulators which output: AVDD 1.8V, AVDD3.3 DRVDD 1.8V, DVDD3.3 DC current consumption –ADC Supply Currents I AVDD < 203 mA –DAC Supply Currents I AVDD < 58mA ADC Analog input signal: –Differential input voltage range: 1.25 Vp-p –Analog Input bandwidth: 70 MHz –Protection from Input over voltage (ESD) ADC External clock input –Clock generator through SMA connector –Min conversion Rate 40 MSPS, 50% duty cycle –Differential Input voltage range < 6 Vp-p

5. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5

6. FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 DATA TO DAC DATA FROM ADC CONFIGURATION USER INTERFACE 50Mhz DE3 OSCILLATOR