1. Figure 2.1. A binary switch. x1=x0= (a) Two states of a switch S x (b) Symbol for a switch

2. Figure 2.2. A light controlled by a switch. (a) Simple connection to a battery S x (b) Using a ground connection as the return path L BatteryLight x Power supply S L

3. Figure 2.3. Two basic functions. (a) The logical AND function (series connection) S x 1 L Power supply S x 2 S x 1 L Power supplyS x 2 (b) The logical OR function (parallel connection) Light

4. Figure 2.4. A series-parallel connection. S x 1 L Power supplyS x 2 Light S x 3

5. Figure 2.5. An inverting circuit. S x L Power supply R

6. Figure 2.6. A truth table for AND and OR.

7. Figure 2.7. Three-input AND and OR.

8. x 1 x 2 x n x 1 x 2  x n +++ x 1 x 2 x 1 x 2 + x 1 x 2 x n x 1 x 2 x 1 x 2  x 1 x 2  x n  (a) AND gates (b) OR gates x x (c) NOT gate Figure 2.8. The basic gates.

9. Figure 2.9. An OR-AND function. x 1 x 2 x 3 fx 1 x 2 +  x 3  =

10. x 1 x 2 1100  f 0001  1101  0011  0101  (a) Network that implements fx 1 x 1 x 2  += x 1 x 2 fx 1 x 2,() 0 1 0 1 0 0 1 1 1 1 0 1 (b) Truth table for f A B Figure 2.10a. Logic network.

11. 1 0 1 0 1 0 1 0 1 0 x 1 x 2 A B f Time (c) Timing diagram 1100  0011  1101  0101  g x 1 x 2 (d) Network that implements gx 1 x 2 += Figure 2.10b. Logic network.

12. Figure 2.11. Proof of DeMorgan’s theorem.

13. Figure 2.12. The Venn diagram representation. Please see “portrait orientation” PowerPoint file for Chapter 2

14. Figure 2.13. Verification of the distributive property. Please see “portrait orientation” PowerPoint file for Chapter 2

15. Figure 2.14. Verification example.

16. Figure 2.15. A function to be synthesized.

17. f (a) Canonical sum-of-products f (b) Minimal-cost realization x 2 x 1 x 1 x 2 Figure 2.16. Two implementations of the function in Figure 2.15.

18. Figure 2.17. Three-variable minterms and maxterms.

19. Figure 2.18. A three-variable function.

20. Figure 2.19. Two realizations of the function in Figure 2.18. f (a) A minimal sum-of-products realization f (b) A minimal product-of-sums realization x 1 x 2 x 3 x 2 x 1 x 3

21. Figure 2.20. NAND and NOR gates.

22. Figure 2.21. DeMorgan’s theorem in terms of logic gates.

23. Figure 2.22. Using NAND gates to implement a sum-of-products.

24. Figure 2.23. Using NOR gates to implement a product-of sums.

25. Figure 2.24. Truth table for a three-way light control.

26. Figure 2.25a. SOP implementation of the three-way light control. f (a) Sum-of-products realization x 1 x 2 x 3

27. Figure 2.25b. POS implementation of the three-way light control. (b) Product-of-sums realization f x 1 x 2 x 3

28. 0000 0010 0101 0111 1000 1011 1100 1111 (a)Truthtable f x 1 x 2 s f s x 1 x 2 0 1 (c) Graphical symbol (b) Circuit 0 1 (d)Morecompacttruth-tablerepresentation sx1x1 x2x2 f (s, x 1, x 2 ) s x1x1 x2x2 Figure 2.26. Multiplexer.

29. Figure 2.27. Screen capture of the Waveform Editor.

30. Figure 2.28. Screen capture of the Graphic Editor.

31. Figure 2.29. The first stages of a CAD system. Please see “portrait orientation” PowerPoint file for Chapter 2

32. Figure 2.30. A simple logic function. f x 3 x 1 x 2

33. Figure 2. 31. Verilog code for the circuit in Figure 2.30. module example1 (x1, x2, x3, f); input x1, x2, x3; output f; and (g, x1, x2); not (k, x2); and (h, k, x3); or (f, g, h); endmodule

34. Figure 2.32. Verilog code for a four-input circuit. module example2 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; and (z1, x1, x3); and (z2, x2, x4); or (g, z1, z2); or (z3, x1, ~x3); or (z4, ~x2, x4); and (h, z3, z4); or (f, g, h); endmodule

35. Figure 2.33. Logic circuit for the code in Figure 2.32.

36. Figure 2.34. Using the continuous assignment to specify the circuit in Figure 2.30. module example3 (x1, x2, x3, f); input x1, x2, x3; output f ; assign f = (x1 & x2) | (~x2 & x3); endmodule

37. Figure 2.35. Using the continuous assignment to specify the circuit in Figure 2.33. module example4 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; assign g = (x1 & x3) | (x2 & x4); assign h = (x1 | ~x3) & (~x2 | x4); assign f = g | h; endmodule

38. Figure 2.36. Behavioral specification of the circuit in Figure 2.30. // Behavioral specification module example5 (x1, x2, x3, f); input x1, x2, x3; output f ; reg f ; always @(x1 or x2 or x3) if (x2 == 1) f = x1; else f = x3; endmodule

39. x 1 x 2 x 3 x 4 (a) x 1 x 2 x 3 x 4 (b) Figure P2.1. Two attempts to draw a four-variable Venn diagram.

40. Figure P2.2. A four-variable Venn diagram.

41. Figure P2.3. A timing diagram representing a logic function. 1 0 1 0 1 0 1 0 x 1 x 2 Time x 3 f

42. 1 0 1 0 1 0 1 0 x 1 x 2 x 3 f Figure P2.4. A timing diagram representing a logic function.