1. Integration and commissioning of the Pile-Up VETO

2. Martin van Beuzekom/ Wilco Vink 212 May 2005 Pile Up system overview

3. Martin van Beuzekom/ Wilco Vink 312 May 2005 System installation / start-up Test optical links –BERT Test of beetle to VEPROB cabling –“static test” –Find copper cable swaps, broken connections etc –Find fiber swaps Tune timing (sampling point) of optical board –Correct for differences in copper cable delay/length Test total Pile-Up VETO system (beetle -> L0DU) –Inject test-pulses (pattern) via beetle: very slow –Use test patterns from VEPROB: fast, but only 4 patterns/VEPROB Tune beetle comparator thresholds With beam: –Tune BCID labeling

4. Martin van Beuzekom/ Wilco Vink 412 May 2005 Optical link test

5. Martin van Beuzekom/ Wilco Vink 512 May 2005 Optical link test Bit error test of optical link –Test optical transmitter, receiver and cable Modularity: 1 optical board (12 links) –Not suited to detect fiber swaps 16 bit pseudo random counter Enable/Disable test via ECS Cannot be interleaved in normal data flow

6. Martin van Beuzekom/ Wilco Vink 612 May 2005 Optional test during installation (pattern generator)

7. Martin van Beuzekom/ Wilco Vink 712 May 2005 Optional test during installation (pattern generator) Find fiber swaps Test optical station inputs Pattern injection at system speed –2k patterns Only 1/8 of input data of complete Pile-Up System –No real trigger decisions (incomplete data) Monitor patterns on VEPROB –L0 buffer via ECS: slow –Via DAQ (through L1 buffer) L0 accepts needed from TFC

8. Martin van Beuzekom/ Wilco Vink 812 May 2005 VETO Connection test

9. Martin van Beuzekom/ Wilco Vink 912 May 2005 VETO connection test Generate “static” test-pattern with beetle output mask (VELO should be installed) Check data routing –Swaps, broken connections etc. Monitor dataflow with: –L0 buffer via CCPC, ECS –L1 buffer TELL1, DAQ Tune timing of optical station –Generate pattern with beetle test-pulse

10. Martin van Beuzekom/ Wilco Vink 1012 May 2005 Timing of Optical Station Correct cable delay diff. and skew Input data @80Mb/s from beetle chips Synchronization selectable via ECS (4 clock phases of 80Mhz) Maximum allowed channel to channel skew: 1 period(12.5 ns)

11. Martin van Beuzekom/ Wilco Vink 1112 May 2005 Pile-Up Algorithm test with VEPROB

12. Martin van Beuzekom/ Wilco Vink 1212 May 2005 Pile-Up Algorithm test with VEPROB Test VEPROB, output board and connection to L0DU 4 event deep memory –Pattern loadable via ECS Real time mode: –Test patterns interleaved with beetle data –Insertion at defined (programmable) BCID Loop mode: –Repetitive pattern, useful for start up test –Pure test patterns, no beetle data Alternative: (slow) –Generate pattern with beetle test-pulse

13. Martin van Beuzekom/ Wilco Vink 1312 May 2005 Beetle Threshold Scan Set Beetle threshold via I2C Fire test-pulse via TFC Capture data from L0 or L1 buffer (preferred) Slow (statistics needed)

14. Martin van Beuzekom/ Wilco Vink 1412 May 2005 With beam

15. Martin van Beuzekom/ Wilco Vink 1512 May 2005 Labeling of data Label data at optical boards –BCID label from counter –(Re)start counter with Bcnt reset –preload value of counter programmable via ECS Lowest 2 bits of BCID on every optical link Full BCID label per 3 links VEPROBs and output board synchronize the data fractions with this BCID label

16. Martin van Beuzekom/ Wilco Vink 1612 May 2005 Monitoring: Histograms on the output board Five different types of bunch crossing can be defined (bx-type) –beam-beam (colliding)2622 x –beam-0 186 x –0-beam 186 x –0-0 570 x –no-data (reset activated etc.) => no histogramming Histogram info from trigger decisions –per bx-type –per BCID

17. Martin van Beuzekom/ Wilco Vink 1712 May 2005 List of histograms Histogram# bins per histogramtype of storage peak 1 position256 bins / bx-type4*256 memory locations peak 1 contents256 bins / bx-type4*256 memory locations peak 2 position256 bins / bx-type4*256 memory locations peak 2 contents256 bins / bx-type4*256 memory locations # vertices / BCID4 bins / BCID3564*4 memory locations # vertices / bx-type4 bins / bx-type4*4 hardwired counters # hits (multiplicity)256 bins / bx-type4*256 memory locations error conditions16 16 memory locations / counters

18. Martin van Beuzekom/ Wilco Vink 1812 May 2005 External systems needed during installation ECS: –SPECs for optical station (and beetle) –Ethernet for CCPC (VEPROB) TFC TELL1 + “DAQ” –Digital –Analog VELO (hybrids) (L0DU)

19. Martin van Beuzekom/ Wilco Vink 1912 May 2005 Status Beetle comparator wafer test –Needs fine tuning –Waiting for green light from Heidelberg group (analog test) Hybrid: –16 Beetle chips mounted: all working –Digital tests done –Analog tests ongoing –Assembly of silicon: soon (weeks) Optical boards –Layout just started VEPROB –Ready for production Output board: –under design

20. Martin van Beuzekom/ Wilco Vink 2012 May 2005 Hybrid testing delayed VELO module mounting ends November 2005 (first half of VELO) –Deadline for first two PU hybrids! VELO installation: October 2006 Planning Pile-Up Schedule TB