1. Teaching Digital Logic courses with Altera Technology
Tutorial #1

2. Learn how to use Quartus:
Outline
Learn how to use Quartus:
Creating projects in Quartus II
Targeting a project for a DE1-SoC Board
Downloading a circuit onto a DE1-SoC board
Compiling and debugging
Overview of tutorials and lab exercises for teaching digital logic using Quartus
Provide context; learn how to use quartus, then talk about teaching materials we have that use quartus

3. Exercise 1: A Simple Quartus Project
Open a Quartus Project
Compile a simple circuit
10-bit shift register
Register input: switch
Shift on key press
Register values displayed on LEDs
Program FPGA with circuit
Examine behavior on the board

4. Step 1: Start Quartus II Project Navigator Status Window
Message Window

5. Step 2: Create a New Project
Click File Menu
Select New Project Wizard
This will open a new window where project information can be specified

6. Project Name and Directory

7. Add Source Files to Project

8. Select the FPGA device on the board
Specify FPGA Device
Select the FPGA device on the board
Cyclone V Family – 5CSEMA5F31C6

9. Specify Tools, in addition to Quartus II, that you will use
Additional EDA Tools
Specify Tools, in addition to Quartus II, that you will use
These are unnecessary for small student designs
Leave all entries as <None>
Press Next

10. New Project Summary

11. Simple Project 10-bit Shift Register … LED[9] LED[2] LED[1] LED[0]
SW[0]
KEY[0]
KEY[1]
Input
Reset_N
Clock
10-bit Shift Register …
LED[9]
LED[2]
LED[1]
LED[0]

12. Step 3: Open Source File
Can open it up by using project navigator. Briefly describe the circuit (SW, key, ledrs connected), some description of the shift register.

13. Step 4: Assign Pins to connect switches/lights to inputs and outputs of your circuit
Click Assignments, then Import Assignments…
Import file
DE1_SoC.qsf
Imports locations for predefined port names, such as SW, LED, KEY, and others
Can be done manually too
Open the file (qsf) and show them LEDR -> mapping to PIN

14. Step 5: Compile Design Placement Timing & Power Synthesis & Routing
Verilog,
VHDL
Synthesis
Placement
& Routing
Timing & Power
Analysis
Assembler
Report
Briefly explain

15. Step 6: Examine Compilation Report
More on pin assignments – look at the board

16. Step 7: Program the Board
Blue LEDs will flash

17. Step 8: See your design work on the board
Press the KEY[0] to clock the circuit
SW[0] is the input to the shift register
Reset the shift register using KEY[1]
Red LEDs
10-bit Shift Register
Input
Reset_N
Clock
SW[0]
KEY[1]
KEY[0]
Replicate the picture from before

18. Please read the instructions at Use provided source code “simple.v”
Hands-On Session
Please read the instructions at
“/Digital Logic/simple/simple_instructions.pdf”
Use provided source code “simple.v”
We will be walking around to help with any issues (such as USB programming)

19. Next Example
Open the Digital Logic folder
Go into stopper subfolder
Open the stopper.qpf Quartus II project

20. Shift the contents of a register once every ~0.1 second
Exercise 2: Stopper
Shift the contents of a register once every ~0.1 second
The circuit is clocked using a 50MHz clock
Press KEY[0] to start or stop the shift register
FSM examines if the key was pressed
Purpose:
Look at FSM implementation in Quartus II
Finite State Machine Viewer

21. Circuit Diagram KEY[0] FSM Clock Divider 10-bit Shift Register Clock
Fast Slow
10-bit Shift Register
enable
Clock
Clock
Picture… 50Mhz counter, counter, SR, FSM. Pressing the key will toggle the FSM state, start/stop the shifting. FSM is used as a puslse generator which gives 1 cycle pulse when key is pressed. ADD toggle flip flop TO THIS PIC (THE REG THAT IS TOGGLED BY FSM)
Red LEDs

22. Step 1: Open Stopper Project

23. Step 2: Compile and Program
Compile the design
Program the design onto the board
How does it work?
Press KEY[0] to start/stop the circuit
Press KEY[1] to reset the circuit

24. Step 3: Examine the FSM Source Code
Add a state diagram before this slide. Briefly describe FSM (3 states, this part gives state transitions, this part gives etc,).

25. Step 4: FSM Viewer Open the FSM Viewer Click Tools
Expand Netlist Viewers
Click State Machine Viewer

26. Examine State Machine
When FSM written properly in accepted way, quartus will detect it and display it here.

27. Please read the instructions at Use provided project “stopper.qpf”
Hands-On Session
Please read the instructions at
“/Digital Logic/stopper/stopper_instructions.pdf”
Use provided project “stopper.qpf”

28. Next Example: Signal Tap II Logic Analyzer
Go into signaltap subfolder
Open the signaltap.qpf Quartus II project
Compile the project, and program the board
Create a virtual logic analyzer in the fabric of the FPGA that can connect to any nodes in the circuit (not just I/O), store the results and display them.

29. SignalTap II Embedded Logic Analyzer
A logic analyzer IP core
Instantiate in your Verilog code
Connects to the board on which a design is running
Collects data when a trigger event occurs
Displays data on your computer

30. SignalTap II Operation
USB-Blaster
cable
FPGA
SignalTap Module
KEY[0]
FSM
KEY[1]
10-bit Shift Register
enable
Clock
Does this thru USB blaster (need no extra tools! No need for expensive logic analyzer).
Clock
Red LEDs

31. Setup SignalTap II Specify cable connection Specify Clock signal
Specify signals
to display

32. For changes to take effect recompile project
Once recompiled, download it to the board
Note: The circuit will be larger than before
Memory is used to store captured data

33. Setup Event Trigger Click here to begin capture
UPDATE screenshot (DE-SoC vs SoCKit)! Sample depth! When the event occurs, it will store the data for x cycles (ex 128 shown) and display the data. Some cycles worth of data before the event as well.

34. Trigger the event and Analyze the results
Use same circuit as previous example (if use previous, LEDS might not shift. Would have to get rid from analyzer).

35. Please read the instructions at Use provided project “signaltap.qpf”
Hands-On Session
Please read the instructions at
“/Digital Logic/signaltap/signaltap_instructions.pdf”
Use provided project “signaltap.qpf”

36. Summary of Tutorial #1 Learned how to Use Quartus II CAD Software
Compile projects in Quartus II
Target design onto DE1-SoC
View results of compilation
Use SignalTap II
Heres what we learned, let me talk about materials you can use for your students

37. Tutorials Tutorials Getting Started with Altera’s DE-series Lab Boards
Introduction to Quartus II
Tutorials
Getting Started with Altera’s DE-series Lab Boards
Introduction to Quartus II
With Verilog, or VHDL, or Schematic
Using library modules (LPMs)
With Verilog or VHDL
Quartus II Simulation
Using ModelSim for Altera
Using TimeQuest Timing Analyzer
Signal Tap II Logic Analyzer
Open up the tutorial, show that it is a complete doc, written like textbook. 37 37 37

38. Digital Logic Lab Exercises
Verilog and VHDL versions
From basic logic gates to simple processors:
Switches, Lights, and Multiplexers
Numbers and Displays
Latches, Flip-flops, and Registers
Counters
Real-time Clock and Timers
Adders, Subtractors, and Multipliers
Finite State Machines
Memory Blocks
A Simple Processor
An Enhanced Processor
Algorithms in Hardware
Digital Signal Processing
Sample curriculum
Set of lab exercises we developed for the digital logic start assuming no knowledge. Simple circuits connecting lights, multiplexers. Later exercises become more advanced and use the simpler circuits from previous exercises, and build more advanced circuits. Fits very well with the way that you would teach a course like this are advanced, not for beginner courses. 38 38 38

39. Lab Exercises and Solutions
Exercises and complete solutions on U.P. web site
Password protected (Professors/Lecturers)
Includes all Quartus II projects
Includes all figures and source text (allows Instructors to add their own material)
RETAKE pic to include exercise 11,12. Also remove part5.Verilog from document_files. We ALSO provide the latex files for the lab writeups so that you can modify them for your course. Mention that we provide verilog AND VHDL solutions and writeups. 39 39 39

40. Organization of Lab Exercises
Simple HDL assignments that directly correspond to Boolean equations
No magic!
Block-based design in which each block of code corresponds to a well-defined subcircuit
HDL code is not a “program”!!
Smaller circuits are built first, and then used to construct larger ones
Good design practice
We though carefully about how to present the exercises to ensure they learn properly. Ex. In first few examples, students cant use advanced verilog features. Can only use boolean eequations. Want students to know they are designing circuits. Type of verilog code we show clearly corresponds to a circuit; easy to see that each part of the code corresponds to circuit. Smaller -> larger, good design practice used in industry. 40 40 40

41. Lab 1: Switches and Lights
/* connect switches to lights through FPGA */
assign light_0 = switch_0;
assign light_1 = switch_1;
. . .
/* build a 2-to-1 multiplexer */
Part 1
Suggested
solution
Part 2
Go through a few slides to give a feeling for the flow of the learning. Lab 1: this is the beginning point. Part 1 assumes students don’t know anything. Open the solution .v. Move on to part 2 the simplest circuit that you can use to build a circuit. 41 41 41

42. … Lab 1 assign m = (~s & x) | (s & y); …
Make 8 copies, connect to 8 red LEDs
Part 2
Suggested
solution
Build a more complex multiplexer:
3-bit wide 5-to-1 multiplexer
Part 3
Suggested
solution
Notice that we are not using IF statements. Use boolean equations to make sure students know what they are doing. 42 42 42

43. … Lab 1 Suggested solution Part 4
7 seg decoder that can display 4 different letters 43 43 43

44. … Lab 1 Make 5 copies of this Suggested solution Part 5 Part 5
Putting together the circuits from the previous parts, you ave the ability to display character patterns. Using only simple 2-1 muxes and a 7-seg decoder, we can make an interesting circuit that can rotate a word across the display. Emphasize hierarchichal fashion small -> larger
Suggested
solution 44 44 44

45. Latches and Flip-flops
Lab 2 and Lab 3
Numbers and Displays
Display binary numbers on 7-segment displays
Convert binary to Binary Coded Decimal
Simple ripple-carry addition
Latches and Flip-flops
Implement RS latch in an FPGA
Implement D latch
Master-slave flip-flop as latches
D registers as Verilog code Clock or negedge Resetn) Q <= R;
As move forward, deal with more complex circuits, display numbers, adders. Start using sequential circuit elements. 45 45

46. Lab 4: Counters assign Enable_0 = SW[1];
Suggested
solution
Part 1
assign Enable_0 = SW[1];
ToggleFF (Enable_0, Clock, Clear, Count_0);
assign Enable_1 = Count_0 & Enable_0;
ToggleFF (Enable_1, Clock, Clear, Count_1);
. . . 46 46 46

47. . . . … Lab 4 /* use some more advanced Verilog */ …
Count <= Count + 1;
Part 2
Suggested
solution
. . .
Count
Part 5
Reusing the circuit from lab 1 that scrolled HELLO, but instead connect a counter instead of SW to do this. Another example of reusing circuits.
Count
Suggested
solution 47 47 47

48. To Students: Write “Obvious” HDL Code
Comparator
assign T = A + B;
(T)
if (T > 9)
begin
Z = 6; C = 1;
end
else
Z = 0; C = 0;
assign S = T + Z;
Adder
Multiplexer that selects
constants
Even when we allow students to use more advanced features of verilog, still make sure each line clearly corresponds to a piece of the circuit. A nice feature of Quartus is to use the RTL viewer to display that the circuit described is actually what you are expecting.
Adder 48 48 48