1. Microprocessor Fundamentals Week 4
Mount Druitt College of TAFE
Dept. Electrical Engineering
2008

2. Review Questions
Briefly state the main difference between dynamic and static RAM.
Explain why it is necessary to regularly refresh the contents of dynamic RAM.
Determine how many address lines are required for a:
2k (2048) RAM. (ie 2k address locations)
16k (65 536) RAM.
32k (32 768) ROM
Briefly explain the meaning of the following terms associated with RAM ICs:
Storage Capacity.
Access Time.
Memory Cell.
Chip Select Input.
Briefly state the main difference between RAM and ROM.
How is an EPROM erased?
What is the main difference between an EPROM and an EEPROM?
The data sheet for a particular ROM states that it has an access time of 250nS. What does this mean and why is it important?
How is a fusible link PROM programmed?
Give one advantage of a Mask Programmed ROM.
What is Flash Memory? Give an example of where it used.
© Mike Stacey 2008

3. Memory Capacity (revised)
A RAM chip has 8 address lines and 8 data lines. What is the memory capacity in bits and bytes?
28 = 256 addresses
256 x 8 bits per location = 2048 bits capacity
2048 bits / 8 = 256 Bytes capacity
A RAM chip has 16 address lines and 8 data lines. What is the memory capacity in bits and bytes?
216 = locations
65536 x 8 bits = 524,288 bits capacity = 65,536 bytes = 64kB
© Mike Stacey 2008

4. Memory Mapping
The location of data going to and coming from I/O devices such as printers comes and goes via a place in memory.
Example:
CPU writes data to memory destined for a modem
CPU reads data from memory which comes from the modem.
Peripherals plus different types of memory (RAM and ROM) are assigned a particular block of memory so the CPU knows where the relevant data or program code is.
© Mike Stacey 2008

5. I/O Ports CPU Main memory Peripheral Device bus Controller port
Diagram adapted from Brookshear (2000): “Computer Science: An Overview”, Addison Wesley
© Mike Stacey 2008

6. Memory Maps (p1)
DFFF
FFFF
BFFF
9FFF
7FFF
5FFF
3FFF
1FFF
Start addresses for each memory segment
ROM (8K)
Unused
I/O
RAM (8K)
C000
E000
A000
8000
6000
4000
2000
0000
End addresses for each memory segment
An address decoding circuit functions to enable the selection of a particular range of addresses…
Figure 4.1 – Memory Map
© Mike Stacey 2008

7. OUTPUTS (only 2 of 8 shown)
Address Decoding (p2)
Remember Decoders?
INPUTS
OUTPUTS (only 2 of 8 shown)
MEMRQ
A15
A14
A13
A12
A11
CS-U2
CS-U1 1
MEMRQ
A15
A14
A13
A12
A11
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
© Mike Stacey 2008

8. Address Decoding (p2) U1 U2 U3 U4 U1: 000 – 7FF U5: 2000 – 27FF
MEMRQ
A15
A14
A13
A12
A11
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 U1 U2 U3 U4
U1: 000 – 7FF
U5: 2000 – 27FF
Each RAM has 11 address lines and 8 data lines: 211 = 2048 x 8 = 2kB capacity
U2: 800 – FFF
U6: 2800 – 2FFF
U3: 1000 – 17FF
U7: 3000 – 37FF
U4: 1800 – 1FFF
U8: 3800 – 3FFF
© Mike Stacey 2008

9. Combinational Decoding (p3)
Figure 4.3 – Memory Address Decoding Using Gates
State the address range for each RAM
© Mike Stacey 2008

10. Review Questions and Practical
Do review questions 1 to 6, section 4.
Do Debug Exercise 4.
Theory and Practical Test 1 next week.
© Mike Stacey 2008