1. HIE REX / ISOLDE New Instrumentation electronics - Main functionalities - S.Burger BI-PM 2014-03-29

2.  1 st design by G.J.Focker & M.Durrafourg in 2010 1 st prototype built but no time for testing since there  Taken from the shelf end of 2013 FPGA code done/tested – VME board validated Some modifications as upgrade (Enrico’specs.) BI/PM internal review in March 2014 New prototype will be ready mid May  VME based  CTRL of stepping motors x8  Acquisition chain x8 Gains CTRLx4 DAC ADC  Integration time (Gate) CTRL 2x2  HV CTRL x2  Compatibility with present ISOLDE scanner hardware AvailableISOLDEREX2 Stepping Motor885 ADC881 DAC1281 Gain444 IT / Gate202 HV201 S.Burger 2014_03_29 Specifications Introduction HIE REX / ISOLDE New Instrumentation electronics - Main functionalities -

3. Scanner 7..0 ISOLDE Scanner Setup VME Board Stepper motor Drivers Preamp. 7..0 Transition module VME BACKPLANE REX Diagnostic Box Setup VME Board Diagnostic Box Up to 5 stepper motors Stepper motor Drivers Preamp. Transition module Amplifier Gain HV Gate VME BACKPLANE Amplifiers CTRL Up to 8 Channels Up to 8 stepper motors CO VME crate (standard) S.Burger 2014_03_29 HIE REX / ISOLDE New Instrumentation electronics - Main functionalities -

4. 8x ADCs, DACs, Voltage reference, Diff.signal receiver VME interface To 8x preamp through P2 (gain CTRL, signal) Powering To/From 8x Stepping driver movements (Steps, Dir, Enable, Switches, etc…) Leds showing stepping status Leds showing VME board status External Trigger External Clock -10 layers -25MHz Quartz ‘Extra’ connector linked to FPGA (available for any upgrade) S.Burger 2014_03_29 HIE REX / ISOLDE New Instrumentation electronics - Main functionalities -

5. DAC ADC FPGA VME Interface Clock Trigger Stepping Driver CTRL Internal Clock Internal Trigger x8 And/Or Or 12 bits 20 bits PreAmp gains CTRL Diff.Signal Input Offset DAC CTRL External ADC CTRL Step Dir Switches Enable Fail… x10, x100 x100Pre x1000Pre MEMORY 1024 pts 32 bits VME Board FPGA: CYCLONE III – EP3C16F484C8N - DeviceEP3C16 Logic elements (LEs)15408 Embedded memory blocks (Kbits)594 PLLs4 Maximum user I/O pins346 Package (mm x mm)UBGA - 19 x 19 Speed Grade8 HIE REX / ISOLDE New Instrumentation electronics - Main functionalities - S.Burger 2014_03_29

6. -EDA-02943-V1-0 -6U format 2 channels with: -HV CTRL -Gain CTRL x4 -Gate (IT) CTRL x2 -Grounding separation Transition module REX Diagnostic box REX S.Burger 2014_03_29 HIE REX / ISOLDE New Instrumentation electronics - Main functionalities -

7. -EDA-02146-V1-0 Transition module ISOLDE scanner -EDA-02145-V1-0 -8 channels -Gain CTRL -Grounding separation -Compatible with present installation External Board ISOLDE scanner ISOLDE S.Burger 2014_03_29 HIE REX / ISOLDE New Instrumentation electronics - Main functionalities -

8. ISOLDE/REX Diagnostic BOX VME Registers VME based synchronous stepping motor driver + ADC for ISOLDE & REX diagnostic boxes Base Address0x200000 Channel addressBits[18:16] [000] is channel 0, [111] is channel 7 NameOffsetWidthDescriptionModeLengthValues Hex Code Version0x000032 Firmware version (0xBB000101) R32 B3= 0xBB B2= 0x01 B1= Version B0= SubVersion Reset0x000432Master resetW-- InternalTrig0x000832Internal trigger for Stepping movement and/or ADC acquisitiomW-- Stepping StartMove0x000C32Start stepping movementW-- StopMove0x001032Stop stepping movementW-- CmdStepNumberReg0x001432Steeping general counterR/W320..0xFFFFFFFF LowSpeedReg0x001832Low speed registerR/W170..0x1FFFF HighSpeedReg0x001C32High speed registerR/W170..0x1FFFF AccDeccRateReg0x002032Rate for acceleration and decelerationR/W190..0x7FFFF RampingDownReg0x002432Ramping down point registerR/W320..0xFFFFFFFF DirectionStepping0x002832Set stepping direction. 0 is '+', 1 is '-'R/W10..1 ResetCounterPos0x002C32Reset counter positionW-- CounterPosition0x003032Counter position taking direction into accountR320..0xFFFFFFFF EnableMoveTrig_r20x003432Bit [1] == 1 enables internal Trigger while [0] ==1 enables external TriggerR/W20..3 ADC StartAcquisition0x007032Start acquisitionW-- ADCClockDivider0x007832Divide 1MHz with selected value of 20 bits. Out clock used for ADC rateR/W200..0x1FFFFF ADCSampleNumber0x007C32Samples general numberR/W110..7FF ADCEnableTrig_r20x008032Bit [1] == 1 enables internal Trigger while [0] ==1 enables external TriggerR/W10..1 StopAcquisition0x008432Stop acquisitionW-- ClockSelect0x008832Select clock source. 1 is internal, 0 is external.R/W10..1 DAC 0x0005032Analogue offset for ADC. Read/Write DAC value 12 bits == +/- 2.5V.R/W120..FFF HV_DAC0x0006032Analogue HV adjustement. Read/Write DAC value 12 bits == +/- 2.5V.R/W120..FFF Status 0x008C32[1] is StepBusy, [0] is ADCBusyR20..3 Gain AmpliGain0x10032Set the 4 bits gainsR/W4 [3]== 1000Pre [2]== 100Pre [1]== x100 [0]== x10 Gate Gate_00x10432Set integration - 12 bits for delay setting and 12 bits for length setting.R/W24 [23:12] Delay - 40ns step [11:0] Length - 40ns step Gate_10x10832Set integration - 12 bits for delay setting and 12 bits for length setting.R/W24 [23:12] Delay - 40ns step [11:0] Length - 40ns step Memory ResetMem0x009032Write 0 in all memoryW32- IndexWrite0x009432Set first address of memoryR/W110..7FF DataRead 00x800032Read Data 0. {StepPos[19:0], Data[11:0]}R320..0xFFFFFFFF …0x8xxx32Read Data xxxx. {StepPos[19:0], Data[11:0]}R320..0xFFFFFFFF DataRead 10430x8FFC32Read Data 1043. {StepPos[19:0], Data[11:0]}R320..0xFFFFFFFF DRAFT S.Burger 2014_03_29 HIE REX / ISOLDE New Instrumentation electronics - Main functionalities -

9. Planning -Production of 2 nd prototype by mid of May -Meanwhile FPGA code to be finished by mid of May -Test bench to be prepared for tests May + June -Launch production of 20 pieces of each module -Should be received and tested by October S.Burger 2014_03_29 HIE REX / ISOLDE New Instrumentation electronics - Main functionalities -