Presentation is loading. Please wait.

Presentation is loading. Please wait.

Capture and record 1GHz signal (Block Diagram)

Published byMarjorie Ball Modified over 8 years ago

Similar presentations

Presentation on theme: "Capture and record 1GHz signal (Block Diagram)"— Presentation transcript:

1 Capture and record 1GHz signal (Block Diagram)
Data Flow structure FADC Fast Analog to Digital Convertor FPGA Choose “Data” DSP “Dig” more VMEbus Data Transfer PC Record & Display 1GHz Analog Signal Function Flow structure Capture (Digitize) Pre-handle (Focus) Handle (Mathematical) Handshake (Transfer) Specification Expand Function Mass Data Real Time Level 1 Cut Pedestal choice MBLT 80MHz Level 2 Cut Width choice Record Time Encode Header, TDC, Trailer

2 Capture and record 1GHz signal (Realized circuit)
Xilinx Spartan-3 XC3S400 500MHz synchronous latch 250MHz synchronous clock XC18V02 National Semiconductor ADC081000 4 ports 8-bits 250MHz MUX 4 ports 8-bits 250MHz FIFO 4 ports 8-bits 250MHz Level 1 Cut Comparator 4 ports 8-bits 250MHz Level 2 Cut Comparator 1GHz Analog Signal 2 ports 8-Bits 500MHz LVDS Data JTAG 1GHz Clock signal 250MHz synchronous clock 8 ports 16-bits 125MHz Encoder Time Counter Trigger 4*32-Bits 125MHz Dual-port RAM 70T3519 TI DSP XC18V01 Xilinx CPLD 125MHz XC95288 Interrupter 5V-3.3V Level change Decoder JTAG SN74LS245 SN74LS245 A01-A31 address, LWORD*, IACK*, AM0-AM5

3 Capture and record 1GHz signal (Power Supply)
3.3V Xilinx Spartan-3 XC3S400 1.2V/2V XC18V02 1.2V/2.5V/3.3V National Semiconductor ADC081000 1GHz Analog Signal JTAG 4*32-Bits 125MHz Dual-port RAM TI DSP 3.3V 5V/3.3V XC18V01 Xilinx CPLD 125MHz XC95288 5V/3.3V JTAG 5V SN74LS245 5V SN74LS245

4 1. VMEBus Backplane supply ±5V, ±12V, GND
2. TI-REG104 supply 2.5V,3.3V (Fixed) with input 5V, current 1A (MAX) (Finished) 2.5/3.3V 3. TI-SN supply 1.2V (Fixed) with input 5V, current 150mA (MAX) 1.2V 4. TI-TPS61020 supply 1.8V-5.5V (Adjustable) with input 5V, current 1.5A (MAX) 2V

5 Capture and record 1GHz signal (Speed Limit)
Xilinx Spartan-3 XC3S400 XC18V02 I/O 622MHz Logic: 326MHz National Semiconductor ADC081000 1GHz Analog Signal 800MHz JTAG 1.6GHz 4*32-Bits 125MHz Dual-port RAM TI DSP 166 MHz XC18V01 Xilinx CPLD 125MHz XC95288 95 MHz JTAG 125 MHz SN74LS245 SN74LS245 80MHz

6 CPLD Download XC18V01 Interrupter Decoder JTAG SN74LS245 SN74LS245
Xilinx CPLD 125MHz XC95288 Interrupter 5V-3.3V Level change Decoder JTAG SN74LS245 SN74LS245 A01-A31 address, LWORD*, IACK*, AM0-AM5

7 VMEbus Handshake XC18V01 Interrupter Decoder JTAG SN74LS245 SN74LS245
Xilinx CPLD 125MHz XC95288 Interrupter 5V-3.3V Level change Decoder JTAG SN74LS245 SN74LS245 A01-A31 address, LWORD*, IACK*, AM0-AM5

Download ppt "Capture and record 1GHz signal (Block Diagram)"

Similar presentations

Interfacing mixed signal peripherals by protocols of packet type Emil Gueorguiev Saramov Angel Nikolaev Popov Computer Systems Department, Technical University.

Interfacing mixed signal peripherals by protocols of packet type Emil Gueorguiev Saramov Angel Nikolaev Popov Computer Systems Department, Technical University.
Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.

Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.
Local Trigger Control Unit prototype

Local Trigger Control Unit prototype
8xADC AMC board Tomasz Klonowski Warsaw University of Technology PERG – ISE 3.12.2007.

8xADC AMC board Tomasz Klonowski Warsaw University of Technology PERG – ISE
Ultrafast 16-channel ADC for NICA-MPD Forward Detectors A.V. Shchipunov Join Institute for Nuclear Research Dubna, Russia

Ultrafast 16-channel ADC for NICA-MPD Forward Detectors A.V. Shchipunov Join Institute for Nuclear Research Dubna, Russia
Implementing Logic Gates and Circuits Discussion D5.1.

Implementing Logic Gates and Circuits Discussion D5.1.
Capstone Fall 2005 GFX-One Guitar Processor Team Carpal Tunnel September 8, 2005.

Capstone Fall 2005 GFX-One Guitar Processor Team Carpal Tunnel September 8, 2005.
Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.

Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.
The Xilinx 95108 CPLD Lecture 4.2. XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s.

The Xilinx CPLD Lecture 4.2. XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s.
IO Controller Module Arbitrates IO from the CCP Physically separable from CCP –Can be used as independent data logger or used in future projects. Implemented.

IO Controller Module Arbitrates IO from the CCP Physically separable from CCP –Can be used as independent data logger or used in future projects. Implemented.
Analog-to-Digital Converters

Analog-to-Digital Converters
1 Color Discriminating Tracking System Lloyd Rochester Sam Duncan Ben Schulz Fernando Valentiner.

1 Color Discriminating Tracking System Lloyd Rochester Sam Duncan Ben Schulz Fernando Valentiner.
Programmable logic and FPGA

Programmable logic and FPGA
Analog-to-Digital Converters Lecture L11.2 Section 11.3.

Analog-to-Digital Converters Lecture L11.2 Section 11.3.
Aztec PC Scope Preliminary Design Review Fall 2006 Michael MasonJed Brown Andrew YoungsJosh Price.

Aztec PC Scope Preliminary Design Review Fall 2006 Michael MasonJed Brown Andrew YoungsJosh Price.
FPGAs and VHDL Lecture L13.1 Sections 13.1 – 13.3.

FPGAs and VHDL Lecture L13.1 Sections 13.1 – 13.3.
Aztec PC Oscilloscope Michael Mason Jed Brown Josh Price Andrew Youngs.

Aztec PC Oscilloscope Michael Mason Jed Brown Josh Price Andrew Youngs.
Implementing Digital Circuits Lecture L3.1. Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable.

Implementing Digital Circuits Lecture L3.1. Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable.
Xilinx CPLDs and FPGAs Lecture L1.1. CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA.

Xilinx CPLDs and FPGAs Lecture L1.1. CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA.
FPGA-Based Systems Design Flow in Action By: Ramtin Raji Kermani.

FPGA-Based Systems Design Flow in Action By: Ramtin Raji Kermani.

Similar presentations

Ads by Google