Reiner Hartenstein University of Kaiserslautern

Reiner Hartenstein University of Kaiserslautern
November 21, 2001, Tampere, Finland Reiner Hartenstein University of Kaiserslautern Enabling Technologies for Reconfigurable Computing Part 4: FPGAs: recent developments Wednesday, November 21, – hrs.

Schedule time slot 08.30 – 10.00 Reconfigurable Computing (RC)
10.00 – 10.30 coffee break 10.30 – 12.00 Stream-based Computing for RC 12.00 – 14.00 lunch break 14.00 – 15.30 Resources for RC 15.30 – 16.00 16.00 – 17.30 FPGAs: recent developments 2

>> Configware Market
FPGA Market Embedded Systems (Co-Design) Hardwired IP Cores on Board Run-Time Reconfiguration (RTR) Rapid Prototyping & ASIC Emulation Evolvable Hardware (EH) Academic Expertise ASICs dead Soft CPU HLLs Problems to be solved 3

Configware heading for mainstream
Configware market taking off for mainstream FPGA-based designs more complex, even SoC No design productivity and quality without good configware libraries (soft IP cores) from various application areas. Growing no. of independent configware houses (soft IP core vendors) and design services AllianceCORE & Reference Design Alliance Currently the top FPGA vendors are the key innovators and meet most configware demand. 4

bleeding edge designs Infinite amount of gates not yet available on a chip 3 mio gates (10 mio in 2003 ?) far away from "infinite" Bleeding edge designs only with sophisticated EDA tools Excessive optimization needed Hardware epertise is inevitable for the designer. improve and simplify the design flow the user provide rich configware libraries of soft IP cores, control appl., networking, wireless telecommunication, data communication, embedded and consumer markets. 5

Configware (soft IP Products)
For libraries, creation and reuse of configware To search for IPs see: List of all available IP The AllianceCORE program is a cooperation between Xilinx and third-party core developers The Xilinx Reference Design Alliance Program The Xilinx University Program LogiCORE soft IP with LogiCORE PCI Interface. Consultants 6

EDA as the Key Enabler (major EDA vendors)
Select EDA quality / productivity, not FPGA architectures EDA often has massive software quality problems Customer: highest priority EDA center of excellence collecting EDA expertise and EDA user experience to assemble best possible tool environments for optimum support design teams to cope with interoperability problems to keep track with the EDA scene as a rapidly moving target being fabless, FPGA vendors spend most qualified manpower in development of EDA, IP cores, applications , support Xilinx and Altera are morphing into EDA companies. 7

OS for FPGAs separate EDA software market, comparable to the compiler / OS market in computers, Cadence, Mentor, Synopsys just jumped in. < 5% Xilinx / Altera income from EDA SW Changing EDA Tools Market Major configware EDA vendors Altera Cadence Mentor Graphics Synopsys Xilinx 8

EDA Software for Xilinx
Full design flow from Cadence, Mentor, & Synopsys Xilinx Software AllianceEDA Program: Alliance Series Development System. Foundation Series Development Systems. Xilinx Foundation Series ISE (Integrated Synthesis Environment) free WebPOWERED SW w. WebFitter & WebPACK-ISE StateCAD XE and HDL Bencher Foundation Base Express Foundation ISE Base Express 9

Foundation ISE Base Express
ModelSim Xilinx Edition (ModelSim XE) Forge Compiler Modular Design Chipscope ILA The Xilinx System Generator XPower JBits SDK The Xilinx XtremeDSP Initiative MathWorks / Xilinx Alliance System Generator Wind River / Xilinx alliance 10

Altera EDA 11 Altera was founded in June 1983
EDA: synthesis, place & route, and, verification Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families MAX+PLUS II: FLEX, ACEX & MAX families Flow with Quartus II: Mentor Graphics, Synopsys, Synplicity deliver a design design software to support Altera SOPC solutions. Mentor: only EDA vendor w. complete design environment f. APEX II incl. IP, design capture, simulation, synthesis, and h/s co- verification Configware: Altera offers over a hundred IP cores Third party IP core design services and consultants 11

Cadence FPGA Designer: top-down FPGA design system,
high-level mapping, architecture-specific optimization, Verilog,VHDL, schematic-level design entry. Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer FPGAs simulated by themselves using Cadence's Verilog-XL or Leapfrog VHDL simulators and simulated w. rest of the system design w. Logic Workbench board/system verification env‘ment. Libraries for the leading FPGA manufacturers. 12

System Design and Verification. PCB design and analysis:
Mentor Graphics System Design and Verification. PCB design and analysis: IC Design and Verification shifts ASIC design flow to FPGAs (Altera, Xilinx) by FPGA Advantage with IP support by ModuleWare, Xilinx CORE Generator Altera MegaWizard integration, 13

Version of ASIC Design Compiler Ultra
Synopsys FPGA Compiler II Version of ASIC Design Compiler Ultra Block Level Incremental Synthesis (BLIS) ASIC <-> FPGA migration Actel, Altera, Atmel, Cypress, Lattice, Lucent, Quicklogic, Triscend, Xilinx 14

>> FPGA Market 15 Configware Market FPGA Market
Embedded Systems (Co-Design) Hardwired IP Cores on Board Run-Time Reconfiguration (RTR) Rapid Prototyping & ASIC Emulation Evolvable Hardware (EH) Academic Expertise ASICs dead Soft CPU HLLs Problems to be solved 15

Top 4 PLD Manufacturers 2000 16 Actel Xilinx Lattice 6% 42% 15% Altera
37% Lattice 15% Actel 6% Top 4 PLD Manufacturers 2000 $3.7 Bio 16

FPGA market 1998 / 1999 38 32 Atmel 8 40 30 Quicklogic 7 43 41 Cypress
6 120 100 Lucent 5 172 154 Actel 4 410 206 Lattice 3 837 654 Altera 2 899 629 Xilinx 1 1999 1998 global sales (mio $) 1999 rank Source: IC Insights Inc. Meanwhile, Xilinx acquired Philips' MOS PLD business, Lattice purchased Vantis. . 17

.... into every application
[Dataquest] PLD market > $7 billion by 2003. „ fastest growing segment of semiconductor market.“ IP reuse and "pre-fabricated" components for the efficiency of design and use for PLDs FPGAs are going into every type of application. 18

.... going into every type of application [Gordon Bell]
19

Xilinx fabless FPGA semi vendor, San Jose, Ca, founded 1984
key patents on FPGAs (expiring in a few years) Fortune 2001: No. 14 Best Company to work for in (intel: no. 42, hp no. 64, TI no. 65). DARPA grant (Nov‘99) to develop Jbits API tools for internet reconfigurable / upgradable logic (w. VT) Less brilliant early/mid 90ies (president Curt Wozniak): 1995 market share from 84% down to 62% [Dataquest] As designs get larger, Xilinx losed its advantage (bugfixes did not require to burn new chips) meanwhile, weeks of expensive debug time needed 20

Xilinx Flexware 21 Virtex, Virtex-II, first w. 1 mio system gates.
Virtex-E series > 3 mio system gates. Virtex-EM on a copper process & addit. on chip memory f. network switch appl. The Virtex XCV3200E > 3 million gates, 0.15-micron technology, Spartan, Spartan-XL, Spartan-II for low-cost, high volume applications as ASIC replacements Multiple I/O standards, on-chip block RAM, digital delay lock loops eliminate phase lock loops, FIFOs, I/O xlators , system bus drivers XC4000XV, XC4000XL/XLA, CPLD: low-cost families rapid development, longer system life, robust field upgradability support In-System Programming (ISP), in-board debugging, test during manufacturing, field upgrades, full JTAG compliant interface CoolRunner: low power, high speed/density, standby mode. Military & Aerospace: QPRO high-reliability QML certified Configuration Storage Devices 21

Altera Flexware Newer families: APEX 20KE, APEX 20KC, APEX II, MAX 7000B, ACEX 1K, Excalibur, Mercury families. Apex EP20K1500E (0.18-µ), up to 2.4 mio system gates, APEX II (all-copper 0.13-µ) f. data path applications, supports many I/O standards. 1-Gbps True-LVDS performance wQ2001, an ARM-based Excalibur device Altera mainstream: MAX 7000A, 3000A; FLEX 6000, 10KA, 10KE; APEX 20K families. Mature and other : Classic, MAX 7000, 7000S, 9000; FLEX 8000, 10K families. 22

Triscend CSoC 23 ARM CSI Socket [Kean]
Digital Filter Display Interface Viterbi A/D Interface CSI Socket ARM Configurable system logic Configurable System Interconnect (CSI) Bus Other System Resources Memory Triscend are currently shipping an 8032 based chip and will release an ARM7 TDMI based chip later this year. The picture shows a Triscend chip implementing the ‘virtual peripherals’ needed in a cellphone application. The first reaction from FPGA people is usually that it is just as good to implement the microcontroller in programmable logic. That way you don’t limit yourself to one microcontroller and its not that many gates…. The problem with this viewpoint is that the Triscend chip is not an FPGA with a microcontroller core --- it’s a microcontroller with ‘virtual’ peripherals. Most users will use a simple drag and drop interface to create exactly the chip they want and the familiar microcontroller development system. No complex ASIC like CAD system is necessary unless you want to develop new ‘virtual peripherals’. The second point is that the CSI bus and large on-chip memory are much less easy to duplicate in programmable logic than the microcontroller core itself. The CSI bus and CSI socket provide a high level memory mapped interface between the virtual peripherals and the microcontroller. 23

>> Embedded Systems (Co-Design)
Configware Market FPGA Market Embedded Systems (Co-Design) Hardwired IP Cores on Board Run-Time Reconfiguration (RTR) Rapid Prototyping & ASIC Emulation Evolvable Hardware (EH) Academic Expertise ASICs dead Soft CPU HLLs Problems to be solved 24

Goal: away from complex design flow
Place and Route Netlist Schematics/ HDL Netlister Bitstream [à la S. Guccione] Compiler HLL 25

Overcome traditional separate design flow
HLL Compiler [à la S. Guccione] User Code Compiler Executable Netlister Netlist Place and Route . Bitstream Schematics/ HDL 26

Overcome traditional co-processing design separate flow -> JBits Design Flow
User Java Code Compiler JBits API Executable [à la S. Guccione] User Code Compiler Executable Netlister Netlist Place and Route . Bitstream Schematics/ HDL 27

Embedded hardw. CPU & memory cores on chip.
HLL Compiler HLL Compiler CPU core FPGA core Memory [à la S. Guccione] 28

new directions in application development
aut. partitioning compilers: designer productivity like CoDe-X (Jürgen Becker, Univ. of Karlsruhe), supports Run-Time Reconfiguration (RTR), a key enabler of error handling and fault correction by partial re-routing the FPGA at run time, as well as remote patching for upgrading, remote debugging, and remote repair by reconfiguration - even over the internet. 29

>> Run-Time Reconfiguration (RTR)

CPU use for configuration management
on-board microprocessor CPU is available anyhow - even along with a little RTOS use this CPU for configuration management Compiler HLL RTR System Design 31

hard CPU & memory core on same chip
Compiler HLL RTR System Design CPU core FPGA core Memory Compiler HLL 32

Converging factors for RTR
Converging factors make RTR based system design viable 1) million gate FPGA devices and co-processing with standard microprocessors are commonplace direct implementation of complex algorithms in FPGAs. This alone has already revolutionized FPGA design. 2) new tools like Xilinx Jbits software tool suite directly support coprocessing and RTR. User Java Code Compiler JBits API Executable 33

RTR divides application into a series of sequentially executed stages, each implemented as a separate execution module. Partial RTR partitions these stages into finer-grain sub-modules to be swapped in as needed. Without RTR, all conf. platforms just ASIC emulators. needs a new kind of application development environments. directly support development and debugging of RTR appl. essential for the advancement of configurable computing will also heavily influence the future system organization Xilinx, VT, BYU work on run-time kernels, run-time support, RTR debugging tools and other associated tools. smaller, faster circuits, simplified hardware interfacing, fewer IOBs; smaller, cheaper packages, simplified software interfaces. 34

Run-time Mapping run-time reconfigurable are: Xilinx VIRTEX FPGA family RAs being part of Chameleon CS2000 series systems Using such devices changes many of the basic assumptions in the HW/SW co-design process: host/RL interaction is dynamic, needs a tiny OS like eBIOS, also to organize RL reconfiguration under host control typical goal is minimization of reconfiguration latency (especially important in communication processors), to hide configuration loading latency, and, Scheduling to find ’best’ schedule for eBIOS calls (C~side). 35

>> Rapid Prototyping & ASIC Emulation

ASIC emulation: a new business model ?
ASIC emulation / Rapid Prototyping: to replace simulation Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor) from rack to board to chip (from other vendors, e. g. Virtex and VirtexE family (emulate up to 3 million gates) Easy configuration using SmartMedia FLASH cards ASIC emulators will become obsolete within years By RTR: in-circuit execution debugging instead of emulation 37

>> Evolvable Hardware (EH)

EH, EM, ... "Evolvable Hardware" (EH), "Evolutionary Methods" (EM), „digital DANN“, "Darwinistic Methods", and biologically inspired electronic systems new research area, also a new application area of FPGAs revival of cybernetics or bionics: stimulated by technology „evolutionary“ and „DNA“ metaphor create awareness EM sucks, also thru mushrooming funds in the EU, in Japan, Korea, and the USA EM-related international conference series are in their stormy visionary phase, like EH, ICES, EuroGP, GP, CEC, GECCO, EvoWorkshops, MAPLD, ICGA 39

EH, EM, ... Shake-out phenomena expected, like in the past with „Artificial Intelligence“ should be considered as a specialized EDA scene, focusing on theoretical issues. Genetic algorithms suck - often replacable by more efficient ones from EDA It is recommendable to set-up an interwoven competence in both scenes, EM scene and the highly commercialized EDA scene EH should be done by EDA people, rather than EM freaks. 40

>> Academic Expertise

BRASS (1) UC Berkeley, the BRASS group: Prof. Dr. John Wawrzynek
The Pleiades Project, Prof. Jan Rabaey, ultra-low power high- performance multimedia computing through reconfiguration of heterogeneous system modules, reducing energy by overhead elimination, programmability at just right granularity, parallellism, pipelining, dynamic voltage scaling. Garp integrates processor and FPGA; dev. in parallel w. compiler - software compile techniques (VLIW SW pipelining): simple pipelining schema f. broad class of loops. SCORE, a stream-based computation model - a unifying computational model. Fast Mapping for Datapaths: by a tree- parsing compiler tool for datapath module mapping 42

BRASS (2) HSRA. new FPGA (& related tools) supports pipelining, w. retiming capable CLB architecture, implemented in a 0.4um DRAM process supporting 250MHz operation OOCG. Object Oriented Circuit-Generators in Java MESCAL (GSRC), the goal is: to provide a programmer's model and software development environment for efficient implementation of an interesting set of applications onto a family of fully-programmable architectures / microarchitectures. 43

Berkeley claiming (1) SCORE, a stream-based computation model: the BRASS group claims having solved the problem of primary impediment to wide-spread reconfigurable computing, by a unifying computational model. Remark: clean stream-based model introduced ~1980: Systolic Array 1995: Rainer Kress. Introduces reconfigurable stream-based model Fast Mapping for Datapaths (SCORE): BRASS claims having introduced 1998 the first tree-parsing compiler tool for datapath module mapping ." Further, it is the first work to integrate simultaneous placement with module mapping in a way that preserves linear time complexity." 44

Berkeley claiming (2) Remark: The DPSS (Data Path Synthesis System) using tree covering simultanous datapath placement and routing has been published in 1995 by Rainer Kress „Chip-in-a-Da2 Bee Project. Prof. Dr. Bob Broderson‘s „radical rethink of the ASIC design flow aimed at shortening design time, relying on stream-based DPU arrays.“ [published in 2000] Remark: the KressArray, a scalable rDPU array [1995] is stream-based 45

.... Stream Processors - MSP-3
3rd Workshop on Media and Stream Processors (MSP-3) in conj. w. 34th Int‘l Symp. on Microarchitecture (MICRO-34) Austin, Texas, December 1-2, 2001 Topics of interest include, but are not limited to: Hardware/Compiler techniques for improving memory performance of media and stream-based processing Application-specific hardware architectures for graphics, video, audio, communications, and other media and streaming applications System-on-a-chip architectures for media & stream processors Hardware/Software Co-Design of media and stream processors and others .... 46

Berkeley: „Chip-in-a-Day“ Bee Project
Chip-in-a-Day Project. Prof. Dr. Bob Broderson, BWRD: targeting a radical rethink of the ASIC design flow aimed at shortening design time. Relying on stream-based DPU arrays (not rDPU and related EDA tools. Davis: „ „... 50x decrease in power requ. over typical TI C64X design.“ New design flow to break up the highly iterative EDA process, allowing designers to spend more time defining the device and far less time implementing it in silicon. „... developers to start by creating data flow graphs rather than C code,„ It is stream-based computing by DPU array (hardwired DPA) For hardwired and reconfigurable DPU array and rDPU array 47

Stanford thru BYU Stanford: Prof. Flynn went emeritus, Oskar Menzer moved to Bell Labs. no activities seen other than YAFA (yet another FPGA application) UCLA: Prof. Jason Cong, expert on FPGA architectures and R& P algorithms. 9 projects, mult. sponsors under California MICRO Program Prof. Majid Sarrafzadeh directs the SPS project: "versatile IPs„, a new routing architecture, architecture-aware CAD, IP-aware SPS compiler USC: Prof. Viktor Prasanna (EE dept.) works 20% on reconfigurable computing: MAARC project, DRIVE project and Efficient Self-Reconfiguration. - Prof. Dubois: RPM Project, FPGA-based emulation of scalable multiprocessors. DEFACTO proj.: compilation - architecture-independent at all levels MIT. MATRIX web pages removed `99. „RAW project“: a conglomerate VT. Prof. Athanas: Jbits API f. internet RTR logic ($2.7 mio DARPA). w. Prof. Brad Hutchings, BYU on programming approaches for RTR Systems BYU. Prof. Brad Hutchings works on the JHDL (JAVA Hardware Description Language) and compilation of JHDL sources into FPGAs. 48

Toronto thru Karlsruhe
U. Toronto. Prof. J.Rose, expert in FPGA architectures and R & P alg. The group has dev. Transmogrifier C, a C compiler creating netlist for Xilinx XC4000 and Altera's Flex 8000 and Flex series FPGAs. Founder of Right Track CAD Corporation acquired by Altera in 1999 Los Alamos National Laboratory, Los Alamos, New Mexico (Jeff Arnold) – Project Streams-C: programming FPGAs from C sources. Katholic University of Leuven, and IMEC: Prof. Rudy Lauwereins, methods for MPEG-4 like multimedia applications on dynamically reconfigurable platforms, & on reconf. instruction set processors. University of Karlsruhe. Prof. Dr.-Ing. Juergen Becker: hardware/software co-design, reconfigurable architectures & rel. synthesis for future mobile communication systems & synthesis w. distributed internet-based CAD methods, partitioning co-compilers 49

>> ASICs dead ? 50 Configware Market FPGA Market
Embedded Systems (Co-Design) Hardwired IP Cores on Board Run-Time Reconfiguration (RTR) Rapid Prototyping & ASIC Emulation Evolvable Hardware (EH) Academic Expertise ASICs dead ? Soft CPU HLLs Problems to be solved 50

(When) Will FPGAs Kill ASICs? [Jonathan Rose]
ASICs Are Already Dead My Position [Jonathan Rose] They Just Don’t Know It Yet! 51

Why? [Jonathan Rose] You have to fabricate an ASIC
Very hard, getting harder An FPGA is pre-fabricated A standard part immense economic advantages You Don’t have fabricate a chip. The FPGA is pre-fabricated. FPGAs are standard parts. 52

Making ASICs is Damn Difficult [Jonathan Rose]
Testing Yield Cross Talk Noise Leakage Clock Tree Design Horrible very deep submicron effects we don’t even know about yet This whole conference is trying to make money helping you get through this nonsense 53

Did I Mention Inventory? [Jonathan Rose]
ASIC users must predict # parts 2 or 3 months in advance! Never guess the Right Amount Make Too Many – You Pay holding costs Make Too Few – Competitor gets the Sale With ASICs, you have to predict the # of chips you need at least 2-3 months in advance! 54 [Jonathan Rose]

[Jonathan Rose] FPGAs Give You
Instant Fabrication Get to Market Fast Fix ‘em quick Zero NRE Charges Low Risk Low Cost at good volume Here we are at DAC – look at all the software people want you to buy so that you can avoid the horrible mess making chips gets you into 55

FPGAs: “Too Pricey & Too Slow ?” [Jonathan Rose]
9 Times Out of 10 You make can the thing fast by breaking it into multiple parallel slower pieces Custom IC Designer Can Make Logic 20x Faster, 20x Smaller than Programmable 56

What’s Wrong with This Picture?
Embedded FPGA Fabric What About PLD Cores on ASICs ? [Jonathan Rose] Still Have to Make the Chip Need Two Sets of Software to Build It The ASIC Flow The PLD Flow Have No Idea What to Connect the PLD Pins to Chances Are, You Are Going to Get It Wrong! 57

What’s Right with This Picture!
Embedded CPU Serial Link, Analog, “etc.” [Jonathan Rose] Pre-Fabricated One CAD Tool Flow! Can Connect Anything to Anything PLDs are built for general connectivity 58

>> Soft CPU 59 Configware Market FPGA Market

Free 32 bit processor core
60

Processors in PLDs: Excalibur
ARM 922T Core General Purpose PLD Dual-Port RAM Single-Port RAM Available Today! [Jonathan Rose] High-Speed Processors Integrated with PLDs Altera XA10 – ARM Core, RAM, PLD on a chip. 61

Soft CPU: new job for compilers
FPGA Memory core Compiler HLL 62

Some soft CPU core examples
Spartan-II 16 bit DSP DSPuva16 FLEX10K30 or EPF6016 i8080A My80 32-bit gr1050 16-bit gr1040 Altera – Mercury 8 bit Nios Altera 22 D-MIPS instr. set 50 MHz Mercury Xilinx up to 100 on one FPGA 32 bit standard RISC 32 reg. by 32 LUT RAM-based reg. MicroBlaze 125 MHz 70 D-MIPS platform architecture core SpartanXL RISC integer C xr16 old Xilinx FPGA Board 16-bit RISC, 2 opd. Instr. YARD-1A 1 Flex 10K20 Acorn-1 Altera, Lattice, Xilinx 8 bit CISC 1Popcorn-1 Lattice 4 isp30256, 4 isp1016 12 bit DSP Reliance-1 2 XILINX 3020 LCA 8 bits Instr. + ext. ROM REGIS 200 XC4000E CLBs CISC, 32 reg. uP bit ARM ARM7 clone SPARC Leon 25 Mhz platform architecture core MircoBlaze vs. Nios: ISE v3.31 vs. Quartus-I v1.0 Virtex II compiles 6 times faster than Mercury and 3 times faster than ApexC Xilinx compiles 1 mio gates in less than one hour See: for: Privatpersonen: YARD-1A, TE16, xr16vx, KIM-RC, PDP-8/X in an XCS10, RISC8 Synthesized PIC, YARD-1A (Yet Another RISC Design), Sparrow (announcement), J32, Reliance-1, PopCorn-1, Acorn-1, private Java processor core: Austin Kim (Lucent), Morris Chang (IIT): Designing A Java ... Private soft CPU: John Rible: Guided Exploration of two FPGA-based CPU Designs MISCs (Minimal Instruction Set Computers) in FPGAs: Novix in an FPGA, MSL16 Processor, P16 in VHDL, Forth Processor in VHDL, E16, 8-bit Stack Processor, FPGA-targetable CPU cores by companies and organizations: Advancel: TinyJ, Altera: Nios, Derivation Systems: LavaCore (Java), Digital Core Design: DR8051, DR8052, D68000, Dolphin Integration: Flip-8051, Ericsson Telecom: ECOMP Erlang processor, Gray Research: xr16, GR CPUs, Green Mountain Computing Systems: GM HC11, Lexra: LX4180, LX4280, LX5280, Nazomi Communications: JStar (Java), Sierra Circuit Design: 65c02, 65cx1, 1802, PIC16C7X, 8085, 6800, 6809, 68HC11, 68000, Silicore: SLC1655, VAutomation: V6502, VZ80, V8-uRISC, V8086, V186, Vulcan: Moon (Java) , Xilinx: KCPSM (8-bit MCU); MicroBlaze (32-bit RISC), Open Source CPU cores et cetera: The Free-IP Project: Free-6502, Free-RISC8, OpenCores: Mini-Risc, OpenRISC 1000, OpenRISC 2000, others Open Collector, LEON SPARC European Space Agency: LEON-1 VHDL Model, Gaisler Research Metaflow's LeonCenter.com Configurable CPU cores hosted in FPGAs: ARCCores: ARC processor Tensilica: Extensa processor Configurable SoCs and FPGAs with hard CPU cores Altera: ARM and MIPS for APEX Atmel: AT94K FPSLIC Field Programmable System Level Integrated Circuits Cypress MicroSystems: PSoC Programmable System-on-a-Chip Triscend: E5 8-bit and A7 32-bit configurable SoCs Xilinx: PowerPC for Virtex-II 63

Nios Architecture (Altera)
64

free DSP or Processor Cores
VHDL Mentor Graphics another i8051 clone i8051 Synopsys 8-bit micro-controller AMD 2910 bit slice AMD 2910 AMD bit slice AMD 2901 i8085 clone GL85 Generic 32-bit RISC CPU DLX2 DLX 6502 compatible core Free-6502 Xilinx XC4000 A 16-bit Harvard DSP with 5 pipeline stages. 16-bit DSP Max2PlusII+ 1 Altera 10k20 small 8 bit CISC Acorn 1 1 Lattice CPLD isp Verilog PopCorn 1 Viewlogic 7 Lattice CPLDs Schematic 12bit DSP and peripherals Reliance 1 Implementation Language Description CPU core 65

FPGA CPUs in teaching and academic research
UCSC: 1990! Märaldalen University, Eskilstuna, Sweden Chalmers University, Göteborg, Sweden Cornell University Gray Research Georgia Tech Hiroshima City University, Japan Michigan State Universidad de Valladolid, Spain Virginia Tech Washington University, St. Louis New Mexico Tech UC Riverside Tokai University, Japan 66

Xilinx 10Mg, 500Mt, .12 mic 67

Soft rDPA feasible ? rDPU Array [à la S. Guccione] 68

data streams, or, from / to embedded memory banks
Array I/O examples data streams, or, from / to embedded memory banks 1 10 100 1000 Performance 1980 1990 2000 µProc 60%/yr.. DRAM 7%/yr.. Processor-Memory Performance Gap: (grows 50% / year) CPU rDPU Array data streams, or, from / to embedded memory banks [à la S. Guccione] 69

soft DPU array HLL 2 Soft Array 70 miscellanous Memory HLL Compiler
soft CPU miscellanous soft DPU array HLL Compiler [à la S. Guccione] 70

rDPU array CPU HLL 2 „flex“ rDPA 71 miscellanous Memory HLL Compiler
[à la S. Guccione] 71

>> HLLs 72 Configware Market FPGA Market

HLLs for Hardware Design vs. System Design vs. RTR System Design
Compiler System Design Compiler HLL RTR System Design [à la S. Guccione] 73

Compiler HLL HLL Compiler System Design Compiler HLL RTR System Design [à la S. Guccione] 74

CPU and memory on Chip 75 HLL FPGA core CPU Memory HLL core Compiler
RTR System Design CPU core FPGA core Memory Compiler HLL [à la S. Guccione] 75

Jbit Environment 76 XHWIF RTP Core Library JRoute API Device Simulator
User Code BoardScope Debugger XHWIF JBits TCP/IP [à la S. Guccione] 76

Compiler HLL HLL Compiler System Design [à la S. Guccione] 77

Embedded System Design
HLL Compiler CPU core FPGA core Memory HLL Compiler soft CPU FPGA Memory core [à la S. Guccione] 78

>> Problems to be solved

Why Can’t Reconfig. Software Survive?
Resource constraints/sizes are exposed: to programmer in low-level representation (netlist) Design revolves around device size Algorithmic structure Exploited parallelism Why can’t RC SW survive? Basic problem is the today’s RC devices are programmed w/exposed resource constraints. i.e. target device size is exposed to programmer and in the low level program representation (netlist). In fact, entire design process revolves around the target device size. Programmer must make decisions to “make sw fit.” Including: algo structure, amount of parallelism. With these decisions made, program is optimized for target device, but does not know how to run on a smaller device, and does not know how to take advantage of additional resources on a larger device. 80

Schedule time slot 08.30 – 10.00 Reconfigurable Computing (RC)
10.00 – 10.30 coffee break 10.30 – 12.00 Stream-based Computing for RC 12.00 – 14.00 lunch break 14.00 – 15.30 Resources for RC 15.30 – 16.00 16.00 – 17.30 FPGAs: recent developments 17.30 end of seminar: thank you for attending 81

Reiner Hartenstein University of Kaiserslautern

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