1. VHDL 1 ©Paul Godin Modified February 2011 Quartus II Version February 2011

2. VHDL VHDL (VHSIC Hardware Description Language) is a standardized programming language used for designing circuits used with CPLDs. VHSIC (Very High Speed Integrated Component). VHDL is a standard described in the IEEE 1076-3 (available here: http://www.accellera.org/ or http://www.standards.ieee.org/ ). http://www.accellera.org/http://www.standards.ieee.org/ Being a standard allows VHDL designs to be transportable. vhdl 1.2

3. Quartus II and AHDL Altera is a leading manufacturer of programmable logic devices.Altera Altera also produces design software including Quartus II. Quartus II belongs to a category of software tools called EDA (Electronic Design Automation). EDA software incorporates device software, analysis tools and physical circuit design. VHDL is an integral part of EDA. Altera utilizes the VHDL standard but also has a modified version, simplified it for its own use: AHDL (Altera Hardware Design Language).Altera AHDL utilizes basic elements and structure of the VHDL standard. vhdl 1.3

4. Text / VHDL design ◊Text/VHDL design is used when graphically designing the circuit is time-consuming or difficult in a graphical format. ◊VHDL is as simple or as complex as the user wants to get. ◊Many aspects of VHDL design resemble other programming languages such as C++. vhdl 1.4

5. Text Editing Advantages of text editing: –Much more flexibility in design, as there are no restrictions to the graphic elements available. –Faster to design a circuit based on input and output criteria. For instance, if a truth table is known, it can be entered directly without conversion to a circuit diagram. Circuit models and templates can be used as guidelines and to speed up code entry. vhdl 1.5

6. VHDL Application Examples ◊Some examples where a problem may be more easily adapted to VHDL: Boolean Expression: 1101 1011 1111 1000 0100 1110 0001 1010 YCBA Truth Table Flowchart: 727234009093049—394-920050884I08i0893930—0220-42kjj9ojio3Ojoo9fc9ioj49\Ojkoj99oou9u9ujj0-\O0-0i04]ii0oi03---943opi230u--293-49-2394858-9-394-9354[u50u2435-9-932=9=2359325’ Program: Decoder vhdl 1.6

7. Utilizes EDIF (Electronic Design Interchange Format) and other design and language standards that are actively maintained by the industry. These designs are portable. Virtual hardware designs can be sent, copied and shared between users and manufacturer platforms. Advantages of Text Editing vhdl 1.7

8. Advantages of VHDL Design ◊Standards-based, transportable to other platforms. ◊Easier for design modifications. ◊Easiest for direct entry of truth table results or Boolean entry. ◊Structure is very similar to other programming languages. ◊Easier for users with an intermediate to advanced digital electronics background. ◊With experience is less time consuming for more complex circuits. ◊Easy to translate flowcharts into a functional circuit design. ◊Greater control of practical issues such as time delays, latency, design changes, etc. ◊With a template or example, can be quite easy to use. vhdl 1.8

9. Disadvantages of VHDL Design ◊Requires an intermediate to advanced background in digital electronics. ◊Requires specific knowledge of the structure and syntax of the language. ◊Recommend some experience with programming languages. ◊May be more difficult to visualize and troubleshoot a design. ◊Some digital processes may be difficult to incorporate into a VHDL design (may be easier to use graphical templates such as shift registers, etc…). vhdl 1.9

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11. Mastering VHDL is not an easy process, and requires extensive study. As with any new programming language, there are different levels of programming mastery. We will look at an introductory approach toward using VHDL/AHDL. Mastering Text Editing Note: Please ensure you have loaded the Quartus II software from Altera and have licensed the software vhdl 1.11

12. 1-Open Quartus II 2-Create a VHDL file: New VHDL File Method for creating a logic design using the Text Editor in Quartus II: vhdl 1.12

13. Device Select 3-Save the file. The software will ask to save the file as a project (may be accepted). On page 3 of 5 enter the device family (MAX7000S) and the Device. Select: EPM7064SLC44-10 Click through the next screens vhdl 1.13

14. Using the Quartus II Software 4- Design the circuit VHDL designs can be relatively simple, and learning VHDL is very similar to learning other programming languages: ◊Greater proficiency comes with study and experience ◊Sample designs can be used as guides to new designs ◊Every detail is important ◊Structuring and proper formatting helps with the design and troubleshooting processes ◊Comments can be added to aid future designers or troubleshooters vhdl 1.14

15. VHDL STRUCTURE vhdl 1.15

16. Text File Basic Structure of VHDL Entity Architecture Defines the inputs and outputs Contains the logic processes Library Defines the source used to translate and resolve the language used in the design process. vhdl 1.16

17. Basic Rules ◊Comment Lines ◊A double-dash precedes comment lines: -- this is a comment line ◊Not case sensitive. Recommend: ◊All caps for VHDL keywords ◊Small letters for variables vhdl 1.17

18. ENTITY: Library Clause ◊Defines the VHDL Library utilized ◊Used with VHDL/AHDL design library IEEE; use IEEE.std_logic_1164.all; The library file contains the source used to convert between the design interface and the device hardware. vhdl 1.18

19. ENTITY: Port ◊A PORT is the input or output of a logic function. ◊Port MODES define whether a value is an input or an output. ◊Port TYPES defines the electrical value the input or output may have. vhdl 1.19

20. Entity: Port MODES IN OUT INOUT BUFFER Input Only Output Only Input or Output (based on a control input) Output with a feedback to internal logic Control vhdl 1.20

21. Entity: Port TYPES U…Un-initialized X…Forcing Unknown 0…Forcing Low 1…Forcing High Z…High Impedance W…Weak Unknown L…Weak Low H…Weak High -…Don’t Care Forcing: Gate output voltage Weak: Used with Pull-up Z: Tri-stated output vhdl 1.21

22. Entity: TYPES TypeValuesQuotesExamples BIT0 or 1Single‘0’, ‘1’ STD_LOGICU,X,0,1,Z,W,L,H,-Single‘0’, ‘1’, ‘Z’,… INTEGERNumbersNone654, -235, 3,… BIT_VECTORBinary number (bit string) Double“10110” STD_LOGIC_VECTORMultiple values for all types Double“0Z1011” “10110” “ZZZZ” vhdl 1.22

23. ENTITY Example: Separate Variables Library IEEE; USE IEEE.std_logic_1164.all; ENTITY sample IS PORT ( a0, a1:INSTD_LOGIC; y0, y1, y2:OUTSTD_LOGIC ); END sample; vhdl 1.23

24. ENTITY Example: Vectors LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY sample IS PORT ( a:INSTD_LOGIC_VECTOR (1 downto 0); y:OUTSTD_LOGIC_VECTOR (2 downto 0) ); END sample; vhdl 1.24

25. ENTITY: Template (from Quartus II software) Note: Fill in what your design requires and delete what isn’t needed. vhdl 1.25 LIBRARY __library_name; ENTITY __entity_name IS GENERIC(__parameter_name : string := __default_value; __parameter_name : integer:= __default_value); PORT( __input_name, __input_name: INSTD_LOGIC; __input_vector_name: IN STD_LOGIC_VECTOR(__high downto __low); __bidir_name, __bidir_name: INOUT STD_LOGIC; __output_name, __output_name: OUTSTD_LOGIC); END __entity_name;

26. Architecture ◊Contains the logic operation of your design. ◊Can be written as: ◊Boolean equations ◊CASE statements (similar to Function/Truth Tables) ◊IF/ELSE statements ◊Other statements (See Templates in the Software) vhdl 1.26

27. Architecture Name ◊The architecture section requires: ◊A name ◊A reference to the entity file ◊BEGIN and END vhdl 1.27

28. Boolean Functions ◊Boolean functions can be entered directly into the Architecture section. ◊Rules of precedence must be forced through the use of brackets. vhdl 1.28

29. Architecture Examples: Boolean ARCHITECTURE sample OF sample1 IS BEGIN y0 <= (a1) and (a0); y1 <= (not a1) and (not a0); y2 <= (not a1) and (a0); END sample Note: A common source of error is unpaired brackets. vhdl 1.29

30. Architecture Examples: Separate Vectors ARCHITECTURE sample OF sample1 IS BEGIN y(0) <= (a(1)) and (a(0)); y(1) <= (not a(1)) and (not a(0)); y(2) <= (not a(1)) and (a(0)); END sample Note: This is assuming the use of vector entity declarations Note: A common source of error is unpaired brackets. vhdl 1.30

31. Architecture Example: CASE Statement ARCHITECTURE sample OF sample1 IS BEGIN y <= “001” WHEN “11”; “010” WHEN “00”; “100” WHEN “01”; “000” WHEN others; END sample Note: This is assuming the use of vector entity declarations. vhdl 1.31

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33. Quartus II ◊Altera’s Quartus II software is complex. It contains advanced features that are well beyond the scope of this course. ◊Its capabilities include the architectural aspects of design, timing and other analysis, special signal handling, and many other logic analysis tools. ◊In this DIGI-2 course we will strictly address how to create and program our device with basic VHDL. vhdl 1.33

34. Pin Planner The Pin Planner window shows the physical layout of the compiled design. The allocation of pins may be done in the Pin Planner window 1.Compile the project 2.Go to the Pin Planner window 3.Check the lines indicated in the Layout menu vhdl 1.34

35. Pin Planner Window vhdl 1.35 Select pins here

36. Pin Planner ◊Once the design has been entered, and the device and pins selected, compile the project. ◊If there are no critical errors, the chip may be physically programmed. vhdl 1.36

37. Report Files ◊The Quartus II compiler produces a report file that describes the results of the compilation processes. ◊Several files ending in.rpt are created. ◊These report files contain information such as the percent utilization of the device, the results of the simplification process and a view of the pin assignments (see the “fit.rpt” file). ◊The files can be reviewed and interpreted using a text editor or by using the Compilation Report button. vhdl 1.37

38. Report Files - Contents Compilation Status: States if the compilation process was successful. Device Summary: States # of pins, Logical Cells, and % of device used. Pin Assignments: States the design to physical pin assignments. Resource Usage, Inputs and Outputs: As implied. Logic Cells: Indicates the internal interconnects between LABs via the PIA. There are many more report options in the Quartus II Application program. Most of these are beyond the scope of this course. vhdl 1.38

39. Equations ◊Quartus II: ◊Open the Tools Menu ◊Select Options ◊General tab, Processing, Automatically generation equation files during compilation vhdl 1.39

40. Report - Equations ◊Open the file xx.fit.eqn using Notepad ◊The Quartus II software determines the Boolean equations for each output. ◊The equations are multi-layered, and additional variables are introduced including the LAB number. ◊The operators are: ◊& = AND ◊# = OR ◊! = Complement ◊$ = Ex-OR vhdl 1.40

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42. VHDL Examples ◊The Quartus II software and Digital Electronics textbooks contain sample code. ◊The following pages contain sample VHDL designs. vhdl 1.42

43. Decoder Example 1 Create a device that will perform the following functions using the Quartus II software. Use: 1.the Graphic Editor 2.the Text Editor vhdl 1.43

44. Decoder Example 2 Create a device that will perform the following functions using the Quartus II software. Use: 1.the Graphic Editor 2.the Text Editor vhdl 1.44

45. Decoder Example 3 Using the Graphic Editor and then the text editor in the Quartus II software, create a device that will perform the following functions: InputOutput ABCXY 00000 00110 01010 01100 10001 10111 11010 11100 vhdl 1.45

46. Decoder Example 4 Using the Graphic Editor and then the text editor in the Quartus II software, create a a BCD to 7-Segment Decoder.Hint: Create a truth table, with BCD as input and 7-Segments (a,b,c,d,e,f,g) as output. See the display diagram below for information. Decoder BCD 7 Segment a b c d e f g vhdl 1.46

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48. Decoder Example 1 Answer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decoder IS PORT( a1, a0: INSTD_LOGIC; y0, y1, y2: OUTSTD_LOGIC ); END decoder; ARCHITECTURE decode OF decoder IS BEGIN y0<=(a1) and (not a0); y1<=(not a1) and (not a0); y2<=(not a1) and (a0); END decode; vhdl 1.48

49. Decoder Example 2 Answer (VHDL) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decoder IS PORT( a2, a1, a0: INSTD_LOGIC; y: OUTSTD_LOGIC ); END decoder; ARCHITECTURE decode OF decoder IS BEGIN y <=((a1) and (not a0))+((a2) and (not a1))+((a2) and (not a0)); END decode; vhdl 1.49

50. Decoder Example 3 Solution Solution: Input the SOP as it appears in the table. InputOutput ABCXY 00000 00110 01010 01100 10001 10111 11010 11100 You may choose to simplify the SOP before entering the Boolean equation in the software, but the compiler will also simplify it. vhdl 1.50

51. Decoder Example 3 Answer (VHDL) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY alarm IS PORT( c, b, a: INSTD_LOGIC; x, y: OUTSTD_LOGIC ); END alarm; ARCHITECTURE table1 OF alarm IS BEGIN x <=((not a) AND (not b) AND (c)) OR ((not a) AND (b) AND (not c) OR ((a) AND (not b) AND (c)) OR ((a) AND (b) and (not c)); y <=((a) AND (not b) AND (not c)) OR ((a) AND (not b) AND (c)); END table1; vhdl 1.51

52. Decoder Example 3 Answer (VHDL) ◊Once the Boolean statements are entered and the design is compiled, the software will simplify the design. ◊This simplified design can be viewed by opening the *.rpt file ◊It may also be seen using the floorplan view and clicking on the outputs. vhdl 1.52

53. Decoder Example 4 Solution Process for the decoder: 1.Create a Truth Table (inputs and outputs) 2.Create a VHDL file Note: using Vector Entities saves time and coding lines. vhdl 1.53

54. Decoder Example 4 Answer (VHDL) Without using vectors in the Entity LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bcd_display IS PORT(d3, d2, d1, d0: INSTD_LOGIC; a, b, c, d, e, f, g: OUTSTD_LOGIC); END bcd_display; ARCHITECTURE decoder OF bcd_display IS SIGNAL input: STD_LOGIC_VECTOR (3 downto 0); SIGNAL output: STD_LOGIC_VECTOR (6 downto 0); BEGIN input <= d3 & d2 & d1 & d0; WITH input SELECT output<= “0000001” WHEN “0000”, “1001111” WHEN “0001”, “0010010” WHEN “0010”, “0000110” WHEN “0011”, “1001100” WHEN “0100”, “0100100” WHEN “0101”, “1100000” WHEN “0110”, “0001111” WHEN “0111”, “0000000” WHEN “1000”, “0001100” WHEN “1001”, “1111111” WHEN OTHERS; a <= output (6); b <= output (5); c <= output (4); d <= output (3); e <= output (2); f <= output (1); g <= output (0); END decoder; vhdl 1.54 Note: There are some small (deliberate) errors in this file

55. Decoder Example 4 Answer (VHDL) Using vectors in the Entity LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bcd_display IS PORT(d: INSTD_LOGIC_VECTOR (3 downto 0); y: OUTSTD_LOGIC_VECTOR (6 downto 0) ); END bcd_display; ARCHITECTURE decoder OF bcd_display IS BEGIN WITH a SELECT y<= “0000001” WHEN “0000”,--segments a to g “1001111” WHEN “0001”, --draws a 1 assuming active low display “0010010” WHEN “0010”, “0000110” WHEN “0011”, “1001100” WHEN “0100”, “0100100” WHEN “0101”, “1100000” WHEN “0110”, “0001111” WHEN “0111”, “0000000” WHEN “1000”, “0001100” WHEN “1001”, “1111111” WHEN OTHERS; END decoder; vhdl 1.55 Note: There are some small (deliberate) errors in this file

56. End ©Paul R. Godin prgodin @ gmail.com vhdl 1.56