1. Customer Presentation ASIC Features ASIC Pricing Immediate Production HDL Design Flow ASIC Features ASIC Pricing Immediate Production HDL Design Flow ASIC Replacement FPGAs FPGA Flexibility at ASIC Prices!

2. Agenda  Spartan Highlights  Advantages vs. Gate Arrays  Spartan Alternative to ASIC Conversions  Spartan Replaces Obsolete Gate Arrays Spartan FPGAs Replace Gate Arrays in Production

4.  1995 - FPGAs cannot compete with gate arrays Older process than ASICs Larger die Not I/O pad limited  1998 - FPGAs compete FPGAs are Fab process drivers, replace DRAMs Competitive die size with similar number of I/O 160 I/O 1998 Gate array, 0.35u, 100K gates SpartanXL, 0.35u, 10K gates Gate Array 0.8u, 10K gates FPGA 1.0u, 5K gates 1995 160 I/O How are Spartan FPGAs Different? Spartan Matches Gate Array Die Size & Cost

5. No Compromises: Performance, RAM, Cores, and Low Price 5 Volt -> 0.5/0.35µ XCS05XCS10XCS20XCS30XCS40 3 Volt -> 0.35/0.25µ XCS05XLXCS10XLXCS20XLXCS30XLXCS40XL System Gates 2K-5K3K-10K7K-20K10K-30K13K-40K Logic Cells23846695013681862 Max Logic Gates 3,0005,00010,00013,00020,000 Flip-Flops 360616112015362016 Max RAM bits 3,2006,27212,80018,43225,088 Max I/O 80112160192224 Performance 80MHz80MHz80MHz80MHz80MHz Xilinx Spartan Series

6. * Source: Dataquest Spartan Features: On-chip SelectRAM™  > 75% ASIC designs need RAM *  SelectRAM advantages: Dual Port Synchronous Higher speed (to 100 MHz) than RAM compilers More flexible - numerous distributed small RAMs

7. Standard Bus Interface Products Peripheral Component Interconnect Bus (PCI) Other Standard Bus Products Digital Signal Processing Correlators Filters Transforms DSP Building Blocks q Spartan Core Advantages: – Pre-verified in silicon – Much lower cost than ASIC cores – Simple distribution and licensing Communications & Networking Products Asynchronous Transfer Mode Forward Error Correction Base-Level Products Basic Elements Math Functions RISC CPU Cores 8-bit RISC core Processor Peripherals UARTs Others Spartan Extensive Core Support

8. High-volume pricing < $3.00* * 100K units 84PLCC, -3 speed Spartan FPGAs Designed for Low Price  Smallest die of any FPGA with RAM  Focused package offering  Streamlined test process  Optimized production flow

9. 5V Price*3V Price** XCS05$3.95$3.50XCS05XL$2.95 XCS10$5.50$4.80XCS10XL$3.95 XCS20$6.50$6.50XCS20XL$5.45 XCS30$7.95$7.95XCS30XL$6.95 XCS40$19.95 $13.80XCS40XL$9.90 * 100K units, end 1998** 100K units, mid 1999 Cheapest pkg, slowest speed NEW Spartan Price Reductions Thru Technology

10. Core Function XCS30XL Price Percentage of Device Used Effective Function Cost UART $6.95 17% $1.20 16-bit RISC Processor $6.95 36% $2.60 16-bit, 16-tap Symmetrical FIR Filter $6.95 27%$1.90 Reed-Solomon Encoder $6.95 6% $0.45 PCI Interface (in PQ208) $8.25 45% $3.80 Cost Effective Cores Replaces Standard Devices

11. 1998 1999 2000 Spartan $3 95* Price SpartanXL $2 95* 0.35  5LM Spartan-II $2 00* 0.5  3LM 2.5 Volt 3.3 Volt 5 Volt * Prices are per 5K system gates, 100K units, slowest speed, 84-PLCC 0.25  5LM 2002 Spartan-III $1 50* 1.8 Volt 0.2  Without Compromises  ASIC prices  Increased density & speed  More SelectRAM TM  Added cores Spartan Cost Reduction Roadmap

13. Spartan Replaces Low-Density Gate Arrays System Gates 50100150200250300 120 100 80 60 40 20 10 0 I/O’s S30 S20 S40 1998 1999 Gate Array Territory High Density, Low I/O Spartan FPGAs Low Density, High I/O S10 Spartan II Spartan I Gates : I/O Fit S05

14. * Manufacturer’s Suggested Resale Price New Car Purchase -- Expected Costs: MSRP* $$$ Hidden costs: Dealer rebates/ holdbacks.. And Unexpected costs: Dealer prep, destination charges, rustproofing …. “Out-the-Door” Costs are Higher! = $$$ Like Buying a New Car Costs of ASIC Design

15. Spartan Avoids Expected Costs

16. Spartan Avoids Unexpected Costs

17. Spartan Avoids Hidden Costs

18. Gate Array Cost Worksheet - New Designs * Assumption: Engineering cost @ $10K man/mo Gate Array Cost*Typical RangeCustomer CostsFPGA Expected costs: NRE cost$15-20K ______________None ATPG from outside service/insert scan10-20K ______________ None Higher cost of ASIC cores50-150K ______________50-70% less Generate & debug testbench10-20K ______________None Unexpected costs: Silicon design iteration (needed in 33-50% of ASIC designs) 15-20K ______________None Extensive customer sign-off (temp, V, MHz sim)10-20K ______________None Expedite prototype/production (hot lot, risk mask, rush assembly)10-40K ______________None Large $ commitment (MOQ, min ship qty, ties up cash)50K+ ______________None Demand slackens (obsolete stock)10-20K ______________None Hidden costs: ASIC production leadtimes (8-10 wks; lost sales, delayed market entry)25K+ ______________None Design change needed in production20K ______________None Scrap obsolete inventory20-30K ______________None Conversion to ASIC costs/risks20K+ ______________None Large ASIC inventory-carrying cost5-15K ______________None Stock multiple ASIC codes: (FPGA single bin stocking)15-20K ______________None Difficult JIT delivery/supply chain management10K+ ______________None Total Gate Array Costs - New Designs$50K-150K ______________ None

20. 198519901995 Year 1980 Design Productivity 2000 Transistors Verilog, VHDL Gates Transistors Gates Behavioral & IP ASIC Methodology FPGA Methodology Schematic Boolean equations Verilog, VHDL RTL Gap FPGAs close the design gap Converging Methodologies

21. ASIC vendor Place & Route ASIC vendor Place & Route ASIC VHDL/Verilog Synthesis Simulation Static timing Fab prototype 4 wk Lead-time Fab prototype 4 wk Lead-time Sign-off Functional simulation Functional simulation Insert Scan Create test vectors Create test vectors ECO Volume Production Volume Production FPGA flow is similar, but: SCAN /test vectors not needed for low densities Built-in JTAG Make mistakes, no penalty Concurrent engineering Real-time verification Not needed with FPGAs Initial production 8-10 wk Lead-time Initial production 8-10 wk Lead-time Customer quote: “FPGAs – I love being able to make mistakes. I can relax and I don’t have to simulate as much. It’s in my control. ASICs – We sweat and don’t sleep much until the ASIC is available and tested.” ” Customer quote: “FPGAs – I love being able to make mistakes. I can relax and I don’t have to simulate as much. It’s in my control. ASICs – We sweat and don’t sleep much until the ASIC is available and tested.” ” Gate Array Design Flow

22. Vendor SimulationSynthesisSchematicOther Synopsys VSS Vital Sim Models FPGA Express FPGA Compiler II Design Compiler DesignWare Motive static timing Cadence Verilog XLSynergyConcept Mentor MTI ModelSim V-System Falcon Framework Viewlogic ViewsimWorkView Spartan Supports Gate Array Tools  Synopsys, Cadence, Mentor, Viewlogic 93% of gate array designers use Synopsys  Support of industry standards EDIF, VITAL, VHDL, Verilog, SDF

23. q Spartan Replaces Gate Arrays  Up to 40K system gates, 224 I/O q Spartan Meets ASIC Requirements mPerformance to 80MHz mOn-chip RAM mSilicon-verified Cores mAggressive volume prices q Spartan FPGAs Avoid ASIC Costs mExpected costs: NRE, scan, test vectors, …. mHidden costs: Leadtimes, inventory design changes, … mUnexpected costs: Spins, sign-off, expediting,.. q HDL Design Flow with Broad 3rd Party Support mSynopsys, Cadence, Mentor, MTI, Synplicity, Exemplar, …. Spartan FPGA Highlights

25. ASICFPGA FPGA-to-ASIC Conversion Direct Translation or Retarget: Engineering costs, Conversion/ NRE fees, 4 month leadtime-to-production, design risks Spartan FPGA into Production No added engineering effort, no NREs, Cost reductions through Spartan II, III, …. Full production NOW! NewParadigm CostlyPath FPGA Cost-Reduction Paths

26. Advantages of FPGAs in Production  ASIC NRE/ Conversion fees Typical range of $5-25K  Customer engineering costs: Verify new gate array design Simulation, test program, sign-off Characterize/ qualify new prototypes Delay work on next project  Lead-times for conversion-to-production a best case of 4 months Conversion time 3 weeks, proto 3 weeks, production 10 weeks = 4 months What is the product life? Is there a mid-life update? Spartan Avoids ASIC Migration Costs & Lead-times

27. Any mistake will exist in final ASIC Design relies on FPGA features  Features not found on ASIC  Example: JTAG, on-chip RAM, global reset, LogiCORE,... Netlist is modified  Often must be modified to add functions  Buffers and clocks are adjusted to optimize drive capability Timing issues  Asynchronous timing  Gated clocks Porting CORES  Timing changes between ASIC/ FPGA  Complex licensing issues  Xilinx / Alliance cores are not transferable Risk Result Spartan Advantage No Unexpected Re-design Risks

28. Gate Array Cost Worksheet - FPGA-to-ASIC Conversion * Assumption: Engineering cost @ $10K man/mo FPGA Conversion Costs*Potential ImpactActualFPGA Costs Expected costs: NRE/conversion fees$15-30K ______________None Verify re-design (sim, vectors, & prototypes)Engineer’s time ______________ None Insert JTAGEngineer’s time ______________None Higher cost of ASIC cores50-150K ______________50-70% less Unexpected costs: 4 months conversion-to-production timeHigher volume ______________None Conversion - 3 weeks needed to Prototype - 3 weeks break even Production delivery - 10 weeks Total time = 16 weeks Hidden costs: Lose reprogrammability advantage More costly changes/ No field updates ______________None Scrap obsolete inventory if design changes20K ______________None Higher inventory costs/levels10K ______________None Conversion re-design risks: Converting FPGA features (RAM, JTAG, reset)Not work in-system ______________ None Modify netlist - new buffers/ new drive capability Not work in-system ______________None Device timing changesNot work in-system ______________None Porting of FPGA CoresDifficult licensing ______________None Total ASIC Costs/Impact - Conversions$50K-100K+ ______________ None

29.  New paradigm - Spartan FPGAs in production Spartan proto to production retains FPGA flexibility Faster, less costly transition to volume production  Cost reduction path with future Spartan Series Spartan II in 1999 Spartan III TBA  Spartan avoids redesign costs to gate array Conversion fees Added customer engineering Long-lead-times for production  Eliminates unexpected migration design risks FPGA features difficult to emulate Net list changes FPGA-to-ASIC Conversion The New Paradigm: FPGAs in Production

31. Exited Gate Array in 1996, FPGA in 1998 No new Gate Array since 1995 HDC Series (1.0  ) H4C Series (0.8  H4CPlus Series (0.65  ) H4EPlus Series (0.65  ) M5C Series (0.5  ) LL7000 Series (2.0  to 10K gates) LL8000 Series (2.0  ) LCA 10000 Compacted Array (to 50K gates ) Leading Suppliers Exit Gate Arrays  Deep sub-micron process increases mask and wafer costs  Accelerates pace to shut down older processes  LSI & Motorola obsolete Gate Array families

32. Memec Responsibility Memec Responsibility Specifications Design files Timing Diagrams Package Rqmts. Quality Stds. Operating Cond. Interface Rqmts. Quantity Schedule Review RFQ Pkg. Business Technical Prepare Quote: Price Delivery Design Reviews Terms Deliverables Responsibilities Create Design Simulate Debug Modify Test Vectors Documentation Verify Design Verify Functionality System Test System Debug Verify Test Vectors Contract Materials from: Insight Memec ICG Quote Package Design Validation Production Customer Responsibility Customer Responsibility RFQPackage Source: Memec Design Services Example Flow Converting Obsolete ASICs to an FPGA

33.  Leading suppliers exit gate arrays Increasing gate array costs LSI Logic and Motorola  Spartan provides low-cost production solution Add/delete features, integrate logic Update design files to Verilog or VHDL for maintainability Long term stable supply No mask charges  Xilinx Certified Design Centers have conversion experience Design centers can provide turnkey service Insight - Memec Design Services Avnet - Design Services Obsolete ASIC to Spartan FPGA “Made Easy”

34.  Spartan meets ASIC requirements ASIC features, pre-verified COREs, aggressive prices, avoids costs of ASIC design and enables flexible production  Supports HDL tools and methodology Broad 3rd party support, flexible design-flow  Provides effective production cost-reduction path Avoids costs and risks of redesign to gate array  Obsolete gate arrays convert to Spartan FPGAs Majors exit gate arrays Conversion to Spartan made easy by Xilinx Design Centers Spartan FPGAs Displace Gate Arrays In Production

36. ASIC Tools ASIC design tool: Synopsys Design Compiler  Synopsys HDL synthesis (93% of designs)  VHDL/ Verilog = 50% shares Synopsys Test Compiler  Scan insertion  Generate test vectors  Increases die size/ impacts performance ASIC Tools ASIC design tool: Synopsys Design Compiler  Synopsys HDL synthesis (93% of designs)  VHDL/ Verilog = 50% shares Synopsys Test Compiler  Scan insertion  Generate test vectors  Increases die size/ impacts performance Spartan Tools FPGA Alternative: Synopsys FPGA Express & FPGA Compiler II Synplicity, Exemplar  New scripts needed Test Compiler Not Needed  Scan is not needed by FPGA  100% factory tested  Test vectors are optional Spartan Tools FPGA Alternative: Synopsys FPGA Express & FPGA Compiler II Synplicity, Exemplar  New scripts needed Test Compiler Not Needed  Scan is not needed by FPGA  100% factory tested  Test vectors are optional Spartan Tool Alternatives

37. ASIC Tools ASIC design tool: RAM compiler  Expands used gates  Lower performance RAM HDL simulators  Cadence VerilogXL  MTI, more…. Static timing  Quad Motive  Synopsys Primetime Cores  In-house  3rd Party ASIC Tools ASIC design tool: RAM compiler  Expands used gates  Lower performance RAM HDL simulators  Cadence VerilogXL  MTI, more…. Static timing  Quad Motive  Synopsys Primetime Cores  In-house  3rd Party Spartan Tools FPGA Alternative: Xilinx compiler  On-chip SelectRAM  No performance impact HDL simulators  Cadence VerilogXL  MTI, more ….. Static timing  Quad Tier 1 in Alliance 2.1  Xilinx Static Timing Cores  LogiCORE  AllianceCORE Spartan Tools FPGA Alternative: Xilinx compiler  On-chip SelectRAM  No performance impact HDL simulators  Cadence VerilogXL  MTI, more ….. Static timing  Quad Tier 1 in Alliance 2.1  Xilinx Static Timing Cores  LogiCORE  AllianceCORE Spartan Tool Alternatives

38. FPGA design optimization requires architectural “know-how” – Complex functions operate > 50MHz – Critical design technique is pipelining FPGA design optimization requires architectural “know-how” – Complex functions operate > 50MHz – Critical design technique is pipelining There Are Design Methodology Differences HDLs were developed for ASICs Achieving 66MHz speed with ASIC is easy FPGAs require more structured techniques HDLs were developed for ASICs Achieving 66MHz speed with ASIC is easy FPGAs require more structured techniques FPGA offer freedom to do design, not under gun till working parts

39. Communications & Networking Products Asynchronous Transfer Mode CRC10 Generator and Verifier (CC-130) CRC32 Generator and Verifier (CC-131) Forward Error Correction Reed-Solomon Decoder Reed-Solomon Encoder Viterbi Decoder Base-Level Products Basic Elements Constant Two Input Multiplexer Three Input Multiplexer Math Functions 1's and 2's Complement Accumulator Scaled by 1/2 Accumulator Registered Adder Registered Loadable Adder Registered Scaled Adder UARTs XF-8250 Asynchronous Communications Element M16450 Universal Asynchronous Receiver/Transmitter Processor Peripherals C2910a Microprogram Controller M8254 Programmable Timer M8255 Programmable Peripheral Interface Extensive Core Support for Spartan Peripheral Component Interconnect Bus (PCI) PCI32 Spartan Master & Slave Interfaces Other Standard Bus Products IIC Digital Signal Processing Correlators One Dimensional RAM Based Correlator One Dimensional ROM Based Correlator Filters Comb Filter 16-Tap, 8-Bit FIR Filter Serial Distributed Arithmetic FIR Filter Dual Channel Serial Distributor Arithmetic FIR Filter Parallel Distributed Arithmetic FIR Filter Transforms DFT Core, (Real Data In, Complex Data Out) FFT Core, (1024 Points) DSP Building Blocks SDA FIR Control Logic Sine/Cosine Processor Products RISC CPU Cores Partial list of Spartan Cores

40. Design: Spartan Gate Array 4Test vectors/ ATPG None Long 4Prototyping time Hours Weeks 4Silicon design changeHours Weeks 4Cost of iterationsNone High 4Cost of CORES Low High Production: 4Fast production rampExcellentPoor 4Lead-timesExcellent Poor 4JIT deliveryExcellentPoor 4React to mkt changesExcellentPoor 4Min order quantitiesLowHigh Inventory: 4 Cost of scrap inventory None High 4 Carrying costsLow High Spartan FPGA Comparison vs. Gate Arrays

41. In Design: 4Eliminates NRE 4Immediate prototypes 4No test vectors/ ATPG needed (100% factory tested) 4No penalty for design spins with reprogrammability 4Broad and verified portfolio of COREs In Production: 4Fast time-to-volume production with “off the shelf” availability 4Immediate market penetration 4Facilitates JIT delivery 4No scrapping inventory 4Enables field product updates FPGA Flexibility at ASIC prices FPGA Flexibility at ASIC prices Spartan Advantages Summary

42. ASIC Replacement FPGAs FPGA Flexibility at ASIC Prices! ASIC Features ASIC Pricing Immediate Production HDL Design Flow ASIC Features ASIC Pricing Immediate Production HDL Design Flow