1. Dual-Pipeline Heterogeneous ASIP Design Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran School of Computer Science & Engineering University of New South Wales, Sydney, Australia Presenters: Firew & Ying Dec 21/2007

2. Dual-pipeline Heterogeneous ASIP Design Slide 2 of 18 Outline Background Motivation Objective and benefit Design scheme –Steps and tools used –The architecture template –Phase I: Target instruction Set Generation –Phase II: Dual Pipeline Instruction Set Creation –Phase III: Dual-Pipeline ASIP construction and code generation Simulation Result Conclusion

3. Dual-pipeline Heterogeneous ASIP Design Slide 3 of 18 Background Embedded systems are now everywhere and continuously growing in capability and complexity. Can be implemented using either GPP, ASIP or ASIC. GPP: –programmable, –availability of tools, –but consume more power –Huge team, manual design ASIC: –low power device, –having a small foot print –but inflexible –complex to design ASIP –compromise solution –Still programmable in the domain –Quick to design –Consume less power than GPP

4. Dual-pipeline Heterogeneous ASIP Design Slide 4 of 18 Motivation Why enhancements on ASIP? 98% of the market of all microprocessors May be constrained by –real-time performance –power utilization, –size and weight –silicon-area –safety –cooling, … Customized design that suits a particular need – increase in performance – reduce power – avoid unnecessary functional units Most researches focus on single-pipeline ASIP One way of enhancement: –enabling multiple instruction issue through a multi-pipeline ASIP design

5. Dual-pipeline Heterogeneous ASIP Design Slide 5 of 18 Objective and benefit Goal : –A two pipeline heterogeneous* ASIP design Benefits: –Exploit parallelism by dual pipelines –improve performance with minimal area penalty –greater design space for the designer –allows code generated for a single pipeline processor to be utilized without major modification –extension to multiple pipeline ASIP processor * Heterogeneity of the processor arises by the differing instruction sets issued to the two pipes

6. Dual-pipeline Heterogeneous ASIP Design Slide 6 of 18 Design Scheme(1/7) ASIP design Process Application/ s processor model OK? more appl.? yes no yes Estimations cycles/alg occupation HW design SW (code generation) Estimations nsec/cycle, area, power/instr go to phase 2 3 phases 1. exploration 2. hw design 3. design appl. sw

7. Dual-pipeline Heterogeneous ASIP Design Slide 7 of 18 Design Scheme(2/7) Basic Steps and Tools Used Assembling: GCC compiler Analyzing and re-ordering Merging Special Instructions generation Target Instruction Set generation Dual-pipeline instruction set generation Two distinct ASIP processors design: ASIPmeiste r Integrating Code generation Simulating: ModelSim and Synplify 3.0.1 Phase I Phase II Phase III

8. Dual-pipeline Heterogeneous ASIP Design Slide 8 of 18 Design Scheme(3/7) The Architecture Template

9. Dual-pipeline Heterogeneous ASIP Design Slide 9 of 18 Design Scheme(4/7) Phase I: Target instruction Set Generation

10. Dual-pipeline Heterogeneous ASIP Design Slide 10 of 18 Design Scheme(5/7) –Phase II: Dual Pipeline Instruction Set Creation

11. Dual-pipeline Heterogeneous ASIP Design Slide 11 of 18 Design Scheme(6/7) Phase II

12. Dual-pipeline Heterogeneous ASIP Design Slide 12 of 18 Design Scheme(7/7) Phase III: Dual-Pipeline ASIP construction and code generation

13. Dual-pipeline Heterogeneous ASIP Design Slide 13 of 18 Simulation

14. Dual-pipeline Heterogeneous ASIP Design Slide 14 of 18 Result(1/2) PNF: Prime Number Finder IS: InSort GCD: Greatest Common Divisor BS: Bubblesort MM: Matrix Multiplication SS: ShellSort

15. Dual-pipeline Heterogeneous ASIP Design Slide 15 of 18 Result(2/2)

16. Dual-pipeline Heterogeneous ASIP Design Slide 16 of 18 Conclusion(1/2) In dual-pipeline ASIP design in comparison to single, a performance improvement of 27.6% and a reduction of switching activity by 6.1% for a number of benchmarks is achieved with an area penalty of about 16%. Allocating load/store operations to one of the pipes and ALU operations to the other pipe is preferred. Simple hardware modules reduces switching activity and hence power

17. Dual-pipeline Heterogeneous ASIP Design Slide 17 of 18 Conclusion(2/2) Availability of synthesis tools and well- flowing design methodology  predictable time-to-market Small design team But design effort seems proportionally growing with complexity of application

18. Dual-pipeline Heterogeneous ASIP Design Slide 18 of 18 Thank you! Questions?