1. http://chess.eecs.berkeley.edu/ February 21, 2008 Center for Hybrid and Embedded Software Systems Mapping A Timed Functional Specification to a Precision Timed (PRET) Machine Abstract Time sensitive tasks such as applying the break in an automobile, or switching tracks at a trail station have increased dependence on hard real-time embedded systems. For years a few programming languages have had the concept of timing, however embedded processors generally use best effort attempts to support timing and lack a direct correlation between timing specified in the programming language and direct support in the embedded architecture used. The PREcision Timed machine was created to guarantee the timing constraints specified in a programming language in the embedded architecture itself. This prompted a mapping from LabVIEW Embedded’s ‘G’ programming language which provides timing specifications to PRET which supports timing constraints. By modifying embedded x86 examples of LabVIEW’s generated C code we were able to successfully run initial experiments on PRET to determine attributes of the processors implementation which could be improved. The experiments pinpointed the need for determinism on PRET’s communication bus, as well as the need for timing analysis to determine the feasibility of multiple concurrent timed tasks without violating timing constraints. It also emphasizes the importance of automating the mapping between a programming language with timing constrains to the PRET processor. This poster presents ongoing research which explores mapping LabVIEW Embedded’s temporal specifications to a prototyped predictable and deterministic embedded processor known as the PREcision Timed Machine (PRET) [1]. Methodology Preliminary Results Future Research Directions Background References Figure 2: Sparc V8 Architecture Figure 1: LabVIEW Tool flow Figure 4: 100us loop output Figure 3: 100us timed loop LabVIEW Tool flow Code is generated from a Virtual Instrument C code runs on target specific runtime libraries Executable is run and signals and output are shown in LabVIEW PRET’s features include: SPARC V8 single core interleaved pipeline architecture. AMBA 2.0 AHB bus interface Seven stage pipeline Deadline instruction incorporated into the ISA to support timing. Modified libraries from an embedded x86 example Manually inserted the assembly deadline instruction Compiled with the sparc tool chain Able to run in simulation of the processor and the FPGA based prototype board. All untimed aspects tested have worked successfully. Hello world, for loops, while loops, sequences, and a single timed loop [1] S. Edwards and E. A. Lee. The case for the precision timed (pret) machine. Technical Report No. UCB/EECS-2006-149, University of California, Berkeley 2006. [2] N. Instruments. Ni labview- the software that powers virtual instrumentation. http://www.ni.com/labview. A Simple Example Shanna Forbes Hiren Patel Hugo Andrade Ben Lickly Isaac Lui http://chess.eecs.berkeley.edu/pret / sssf@eecs LabVIEW allows users to quickly create software for multiple platforms without changing their graphical programs. PRET is an embedded processor architecture which supports predictable timing without foregoing performance. Model Functional and Architectural Variations Non-determinism in the bus Modeled Functional and Architectural Variations Complete the mapping of LabVIEW Embedded’s platform-based design methodology to PRET’s single core architecture. i.e.. Loading a deadline directly into a register. Implement concurrency through threads IE. Map parallel timed loops to multiple threads Complete timing Analysis of software for PRET machines Map the flags on errors in PRET to the errors in LabVIEW during pre-compilation. Program PRET automatically from LabVIEW