1. Accessing I/O Devices
Processor
Memory
BUS
I/O Device 1
I/O Device 2

2. Comments about last slide
Simplest of arrangements to connect I/O devices to a computer
Single Bus
Three sets of lines
Address, data, control
Processor requests read or write operation on control lines, data is transferred over data lines

3. Bus Connection for Processor, Keyboard and Display

4. Comments about last slide
DataIn is a 8-bit buffer register
SIN is a status control flag to inform the processor that a valid character is in DataIn.
A program monitors SIN, and when SIN is set to 1, the processor reads the contents of DATAIN. When the character is transferred to the processor, SIN is set to 0.
Process continues for each character entered on keyboard.
This process is called Program-controlled I/O.
Same process would occur for output to display.

5. Memory-Mapped I/O I/O Devices and memory share the same address space.
Each I/O Device is assigned a unique set of addresses.
Many computers use memory address values to refer to peripheral device buffer registers such as DATAIN and DATAOUT.
When the processor places a particular address on the address lines, the device recognizing this address responds to the commands on the control lines.
The processor requests either a read or a write operation, and the requested data is transferred over the data lines.
Any machine instruction that can access memory can be used to transfer data to/from I/O devices.
Mov DATAIN, R0

6. Memory Mapped I/O
When I/O devices and the memory share the same address space.
Intel processors have special I/O instructions and a separate 16-bit address space for I/O devices.
Designer has choice of using special I/O address space or incorporating I/O devices into memory address space.

7. Hardware Required for an I/O Interface for an Input Device

8. Hardware Address Decoder Data Register Status Register
enables device to recognize its address when address appears on address lines
Data Register
Holds data being transferred to or from processor
Status Register
Contains information relevant to the operation of the I/O device
Hardware is called device’s interface circuit

9. Registers in Keyboard and Display Interfaces

10. Example of Last Slide
Register STATUS contains two control flags, SIN and SOUT,two interrupt flags, KIRQ and DIRQ (keyboard interrupt request and display interrupt request). The control register has two bits, DEN and KEN (Display enable and Keyboard Enable) which are used to enable the data lines to each interface circuit.

11. Program-Controlled I/O
This example illustrates program-controlled I/O in which the processor repeatedly checks the status flag to achieve the required synchronization between the processor and an input or output device.

12. Program to read data from keyboard, store it in the memory buffer, and echo it back to the display.

13. Ways to Drive Hardware Devices
Programmed I/O
Interrupt I/O
Direct Memory Access

14. Programmed I/O (driving Hardware devices through I/O ports)
External devices are almost always connected not directly to the system bus but to an INTERFACE.
Registers in the interface allow for a wide range of possibilities for the designer to determine how it is to interface to the bus.
TO avoid confusion with the main registers in the 8086, peripheral interface chip registers are usually referred to as PORTS.

15. Interface Ports Typically consists of three registers
Control Port - the setting of which will determine if the interface is to send or receive.
Data Port – for the data element to be transmitted or to hold a data element received.
Status Port – used to obtain information such as “printer out of paper, don’t send any more data” or, for a serial transmission, “all the bits of the data element haven’t yet been received”
Simple interfaces may have status and control combined into one port; sophisticated ports may have multiple control and status ports.

16. Intel Architecture
Intel processors have a separate 16-bit address bus for I/O devices
Designer has the option of
connecting I/O devices to use special address space
or simply incorporating them as part of the memory address space.
The later approach leads to simpler software.
One advantage of a separate address bus for I/O is reduced number of address lines needed for I/O devices.
Not physically separate address lines on processor. Special signal (I/OR or I/OW, MemR or MemW)

17. I/O Interface for an Input Device
Address Lines
Data Lines
Control Lines
Address
Decoder
Control
Circuits
Data and
Status Registers
I/O Interface
Input Device

18. I/O Device Speeds
Processors can operate at speeds that are vastly different than I/O speeds.
When a human is entering characters on a keyboard, the processor can execute millions of instructions between successive character entries.
So, how does the processor handle I/O inputs…..

19. Three types of I/O Strategies
Polled I/O
Interrupt Driven I/O
DMA I/O

20. Polled IO versus Interrupt Driven I/O
Polled IO – processor continually checks IO device to see if it is ready for data transfer
Inefficient, processor wastes time checking for ready condition
Interrupt Driven IO – IO device interrupts processor when it is ready for data transfer
Processor can be doing other tasks while waiting for last data transfer to complete – very efficient.

21. I/O Interfacing
A lot of handshaking is required between the CPU and most I/O devices.
All I/O devices operate asynchronously with respect to the CPU. The events that determine when an input device has data available or when an output device needs data are independent of the CPU.

22. Three I/O strategies
Must be capable of data rates fast enough to keep up with the demands of the device, but must not be allowed to transfer data faster than the device can process it.
Polled waiting loops
Interrupt-driven I/O
Direct memory Access (DMA)

23. Synchronization
The CPU must have some way of checking the status of the device and waiting until it is ready to transfer

24. Transfer Rate
A measure of the number of bytes per second transferred between the CPU and an external device.
Maximum transfer rate – a measure of the bandwidth capability of a particular method of doing I/O.

25. Comparison of transfer rates
Polled waiting loops provide data rates that are a bit slower, but still quite reasonable.
Interrupt-driven I/O requires overhead of saving and restoring the machine state (significantly degrades data rates unless more than one byte can be transferred per interrupt.
DMA has fastest transfer rates (additional hardward complexity needed.

26. Latency
Measure of the delay from the instant that the device is ready until the time the first data byte is transferred. Latency is equivalent to the “response time”

27. Comparison of Latency
Polled Waiting Loops – latency can be very high (the computer may not even be checking the device for new data when it arrives).
Interrupt-driven I/O – dramatically lower than polled, but still imposes a software overhead.
DMA – very low (lower than the others)

28. Polled Waiting I/O
Use software to test the status of a device,before transferring each data byte.
Continuously checking the peripheral’s BUSY/READY flag
Ties up the CPU – no other tasks can be performed.

29. Interrupt-Driven I/O There are different types of interrupts Hardware
Generated by the 8259 PIC – signals the CPU to suspend execution of the current program and process the interrupt (keyboard, serial port)
Occasionally, programs must disable hardware interrupts when performing sensitive operations on segment registers and the stack. Use CLI (Clear Interrupt flag) to disable interrupts and STI (Set interrupt flag) to enable interrupts.
Software
Not really an interrupt (INT)
Internal Interrupts
Divide by zero
Traps

30. Responding to Interrupts

31. Hardware Interrupt Pins
NMI – non-maskable interrupt – it cannot be blocked (the CPU must respond) – reserved for critical system functions.
INTR – maskable via the IF flag.