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Unit-5 CO-MPI autonomous

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1 Unit-5 CO-MPI autonomous
Input/Output Unit-5 CO-MPI autonomous

2 Contents: External Devices I/O Modules Programmed I/O
Interrupt Driven I/O Direct Memory Access I/O Channels and Processors Asynchronous Data Transfer Interrupt and Interrupt Vectors

3 Input/Output Problems
Wide variety of peripherals Delivering different amounts of data At different speeds In different formats All slower than CPU and RAM Need I/O modules

4 Input/Output Module Interface to CPU and Memory
Interface to one or more peripherals

5 Generic Model of I/O Module

6 1. External Devices Human readable Machine readable Communication
Screen, printer, keyboard Machine readable Monitoring and control Communication Modem Network Interface Card (NIC)

7 External Device Block Diagram

8 2. I/O Module Function Control & Timing CPU Communication
Device Communication Data Buffering Error Detection

9 I/O Steps CPU checks I/O module device status
I/O module returns status If ready, CPU requests data transfer I/O module gets data from device I/O module transfers data to CPU Variations for output, DMA, etc.

10 I/O Module Diagram

11 I/O Module Decisions Hide or reveal device properties to CPU
Support multiple or single device Control device functions or leave for CPU Also O/S decisions

12 Input Output Techniques
Programmed Interrupt driven Direct Memory Access (DMA)

13 Three Techniques for Input of a Block of Data

14 3. Programmed I/O CPU has direct control over I/O
Sensing status Read/write commands Transferring data CPU waits for I/O module to complete operation Wastes CPU time

15 Programmed I/O - detail
CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU directly I/O module does not interrupt CPU CPU may wait or come back later

16 I/O Commands CPU issues address CPU issues command
Identifies module (& device if >1 per module) CPU issues command Control - telling module what to do e.g. spin up disk Test - check status e.g. power? Error? Read/Write Module transfers data via buffer from/to device

17 Addressing I/O Devices
Under programmed I/O data transfer is very like memory access (CPU viewpoint) Each device given unique identifier CPU commands contain identifier (address)

18 I/O Mapping Memory mapped I/O Isolated I/O Limited set
Devices and memory share an address space I/O looks just like memory read/write No special commands for I/O Large selection of memory access commands available Isolated I/O Separate address spaces Need I/O or memory select lines Special commands for I/O Limited set

19 4. Interrupt Driven I/O Overcomes CPU waiting
No repeated CPU checking of device I/O module interrupts when ready

20 Interrupt Driven I/O Basic Operation
CPU issues read command I/O module gets data from peripheral whilst CPU does other work I/O module interrupts CPU CPU requests data I/O module transfers data

21 CPU Viewpoint Issue read command Do other work
Check for interrupt at end of each instruction cycle If interrupted:- Save context (registers) Process interrupt Fetch data & store

22 Simple Interrupt Processing

23 Changes in Memory and Registers for an Interrupt

24 Design Issues How do you identify the module issuing the interrupt?
How do you deal with multiple interrupts?

25 Identifying Interrupting Module (1)
Different line for each module Limits number of devices Software poll CPU asks each module in turn Slow

26 Identifying Interrupting Module (2)
Daisy Chain or Hardware poll Interrupt Acknowledge sent down a chain Module responsible places vector on bus CPU uses vector to identify handler routine Bus Master Module must claim the bus before it can raise interrupt

27 Multiple Interrupts Each interrupt line has a priority
Higher priority lines can interrupt lower priority lines If bus mastering only current master can interrupt

28 Example - PC Bus 80x86 has one interrupt line
8086 based systems use one 8259A interrupt controller 8259A has 8 interrupt lines

29 Sequence of Events 8259A accepts interrupts 8259A determines priority
8259A signals 8086 (raises INTR line) CPU Acknowledges 8259A puts correct vector on data bus CPU processes interrupt

30 82C59A Interrupt Controller

31 Intel 82C55A Programmable Peripheral Interface

32 Keyboard/Display Interfaces to 82C55A

33 5. Direct Memory Access Interrupt driven and programmed I/O require active CPU intervention Transfer rate is limited CPU is tied up DMA is the answer

34 DMA Function Additional Module (hardware) on bus
DMA controller takes over from CPU for I/O

35 Typical DMA Module Diagram

36 DMA Operation CPU tells DMA controller:-
Read/Write Device address Starting address of memory block for data Amount of data to be transferred CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished

37 DMA Transfer Cycle Stealing
DMA controller takes over bus for a cycle Transfer of one word of data Not an interrupt CPU does not switch context CPU suspended just before it accesses bus i.e. before an operand or data fetch or a data write Slows down CPU but not as much as CPU doing transfer

38 DMA and Interrupt Breakpoints During an Instruction Cycle

39 DMA Configurations (1) Single Bus, Detached DMA controller
Each transfer uses bus twice I/O to DMA then DMA to memory CPU is suspended twice

40 DMA Configurations (2) Single Bus, Integrated DMA controller
Controller may support >1 device Each transfer uses bus once DMA to memory CPU is suspended once

41 DMA Configurations (3) Separate I/O Bus
Bus supports all DMA enabled devices Each transfer uses bus once DMA to memory CPU is suspended once

42 Intel 8237A DMA Controller Interfaces to 80x86 family and DRAM
When DMA module needs buses it sends HOLD signal to processor CPU responds HLDA (hold acknowledge) DMA module can use buses E.g. transfer data from memory to disk Device requests service of DMA by pulling DREQ (DMA request) high DMA puts high on HRQ (hold request), CPU finishes present bus cycle (not necessarily present instruction) and puts high on HDLA (hold acknowledge). HOLD remains active for duration of DMA DMA activates DACK (DMA acknowledge), telling device to start transfer DMA starts transfer by putting address of first byte on address bus and activating MEMR; it then activates IOW to write to peripheral. DMA decrements counter and increments address pointer. Repeat until count reaches zero DMA deactivates HRQ, giving bus back to CPU

43 8237 DMA Usage of Systems Bus

44 Fly-By While DMA using buses processor idle
Processor using bus, DMA idle Known as fly-by DMA controller Data does not pass through and is not stored in DMA chip DMA only between I/O port and memory Not between two I/O ports or two memory locations Can do memory to memory via register 8237 contains four DMA channels Programmed independently Any one active Numbered 0, 1, 2, and 3

45 6. I/O Channels and Processors
I/O devices getting more sophisticated e.g. 3D graphics cards CPU instructs I/O controller to do transfer I/O controller does entire transfer Improves speed Takes load off CPU Dedicated processor is faster

46 I/O Channel Architecture

47 7. Asynchronous Data Transfer
Synchronous and Asynchronous Operations Synchronous - All devices derive the timing information from common clock line Asynchronous - No common clock Asynchronous Data Transfer Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted. Two Asynchronous Data Transfer Methods Strobe pulse - A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to occur Handshaking - A control signal is accompanied with each data being transmitted to indicate the presence of data - The receiving unit responds with another control signal to acknowledge receipt of the data.

48 Strobe Control * Employs a single control line to time each transfer
* The strobe may be activated by either the source or the destination unit Source-Initiated Strobe for Data Transfer Destination-Initiated Strobe for Data Transfer Block Diagram Block Diagram Data bus Data bus Source Destination Source Destination unit Strobe unit unit Strobe unit Timing Diagram Timing Diagram Valid data Valid data Data Data Strobe Strobe

49 Handshaking Strobe Methods Source-Initiated
The source unit that initiates the transfer has no way of knowing whether the destination unit has actually received data. Destination-Initiated The destination unit that initiates the transfer no way of knowing whether the source has actually placed the data on the bus. To solve this problem, the HANDSHAKE method introduces a second control signal to provide a Reply to the unit that initiates the transfer

50 Source-Initiated Transfer Using Handshake
Data bus Data valid Block Diagram Source Destination unit Data accepted unit Data bus Valid data Timing Diagram Data valid Data accepted Sequence of Events Source unit Destination unit Place data on bus. Enable data valid. Accept data from bus. Enable data accepted Disable data valid. Invalidate data on bus. Disable data accepted. Ready to accept data (initial state). * Allows arbitrary delays from one state to the next * Permits each unit to respond at its own data transfer rate * The rate of transfer is determined by the slower unit

51 Destination –Initiated Transfer Using Handshake
Data bus Block Diagram Data valid Source Destination Ready for data unit unit Ready for data Timing Diagram Data valid Data bus Valid data Sequence of Events Source unit Destination unit Ready to accept data. Place data on bus. Enable ready for data. Enable data valid. Accept data from bus. Disable data valid. Disable ready for data. Invalidate data on bus (initial state). * Handshaking provides a high degree of flexibility and reliability because the successful completion of a data transfer relies on active participation by both units * If one unit is faulty, data transfer will not be completed -> Can be detected by means of a timeout mechanism

52 Asynchronous Serial Transfer
Asynchronous parallel transfer Synchronous parallel transfer Four Different Types of Transfer Asynchronous Serial Transfer - Employs special bits which are inserted at both ends of the character code - Each character consists of three parts; Start bit; Data bits; Stop bits. 1 1 1 1 Start Stop Character bits bit (1 bit) bits (at least 1 bit) A character can be detected by the receiver from the knowledge of 4 rules; - When data are not being sent, the line is kept in the 1-state (idle state) - The initiation of a character transmission is detected by a Start Bit , which is always a 0 - The character bits always follow the Start Bit - After the last character , a Stop Bit is detected when the line returns to the 1-state for at least 1 bit time The receiver knows in advance the transfer rate of the bits and the number of information bits to expect

53 Universal Asynchronous Receiver-Transmitter - UART
A typical asynchronous communication interface available as an IC Transmit Bidirectional Transmitter Shift data data bus Bus register register buffers Control Transmitter Transmitter clock register control and clock Chip select CS Internal Bus Register select RS Timing Status Receiver Receiver CS RS Oper. Register selected x x None WR Transmitter register WR Control register RD Receiver register RD Status register register control clock I/O read and and clock RD Control I/O write Receive WR Receiver Shift data register register Transmitter Register - Accepts a data byte(from CPU) through the data bus - Transferred to a shift register for serial transmission Receiver - Receives serial information into another shift register - Complete data byte is sent to the receiver register Status Register Bits - Used for I/O flags and for recording errors Control Register Bits - Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of stop bits

54 8. Interrupt and Interrupt Vectors
In the Interrupt Initiated I/O the CPU responds to the interrupt signal by storing the return address from the program counter into a memory stack and then control branches to a service routine that processes the required I/O transfer. The way that the processor chooses the branch address of the service routine varies from one unit to another. In principle, there are two methods for accomplishing this Vectored interrupt Non-Vectored interrupt

55 Interrupt and Interrupt Vectors
Non Vectored Interrupt The branch address is assigned to a fixed location in memory. Vectored Interrupt The source that interrupts supplies the branch information to the computer. This information is called the interrupt Vector. In some computers the interrupt vector is the first address of the I/O service routine. In other computers the interrupt vector is an address that points to a location in memory where the beginning address of the I/O service routine is stored.

56 The End

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