1. FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved ASIC to FPGA Coding Conversion, Part 1

2. Fundamentals of FPGA Design 1 day Designing for Performance 2 day s Advanced FPGA Implementation 2 days Intro to VHDL or Intro to Verilog 3 days FPGA and ASIC Technology Comparison FPGA vs. ASIC Design Flow ASIC to FPGA Coding Conversion Virtex-5 Coding Techniques Spartan-3 Coding Techniques CurriculumPath for ASIC Design FPGA and ASIC Technology Comparison

3. Welcome If you are an experienced ASIC designer transitioning to FPGAs, this course will help you reduce your learning curve by leveraging your ASIC experience Careful attention to how a design can be optimized for an FPGA, will help you create a fast and reliable FPGA design

4. Optimize ASIC code for implementation in an FPGA Describe the steps to perform ASIC to FPGA code conversion After completing this module, you will able to:

5. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2009 Xilinx, Inc. All Rights Reserved Xilinx FPGA Optimization To obtain the desired performance and area goals, the design needs to be optimized for a Xilinx FPGA Xilinx FPGAs contain special resources that provide for better performance and optimization DCM, block RAM, global clock routing resources, and clock enable ports, for example Use synchronous design methodology for performance and reliability Some resources need to be instantiated Some resources cannot be inferred Startup block, DCM, and SelectIO™ interfaces, for example

6. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2009 Xilinx, Inc. All Rights Reserved Xilinx-Specific Resources Inference Check your synthesis tool’s solutions database—often best for primary logic resources Instantiation (from the Architecture Wizard) Best for SERDES (ChipSync™ Wizard), DCM (DCM Wizard), or PLL components Instantiation (from the Core Generator™ tool) Best for DSP, block RAM, larger components, and custom components Instantiation (from the Memory Interface Generator) Best for memory controllers Instantiation (from the Xilinx Unified Library) Best for startup blocks, I/O buffers, or ANY resource

7. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2009 Xilinx, Inc. All Rights Reserved Instantiation Rules Rule of thumb: Instantiate only when you cannot infer a proper resource or when inference does not provide acceptable results Each synthesis tool requires different resources to be instantiated, while others can infer resources if an additional synthesis tool attribute is applied So check your vendors solution data base (Exemplar, Synopsys, and XST)

8. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2009 Xilinx, Inc. All Rights Reserved Synthesis Settings Synthesis tools help you to achieve higher performance by Duplicating registers and logic to reduce fanout Extracting state machines to re-encode for one-hot, gray, binary, or two-hot encoding Replicating the IOB three-state register Allows the register to be placed in the IOB by providing faster clock-to-out Optimizing for area or speed on a module-by-module basis Providing constraint-driven optimization (Synopsys, Exemplar, and XST)

9. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2009 Xilinx, Inc. All Rights Reserved Xilinx-Specific Code Separate Xilinx-specific code and instantiations from the generic HDL Allows easier migration to other technologies At the top-level, create a Xilinx “wrapper” to instantiate SelectIO interface buffers or DCMs As well as any other top-level, Xilinx-specific instantiations BUFGs (global clock buffers) Block RAMs Cores (optimized components from the Core Generator tool) At the sub-block level, create Xilinx-specific hierarchical blocks for Xilinx- specific code

10. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2009 Xilinx, Inc. All Rights Reserved Xilinx-Specific Hierarchy

12. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2009 Xilinx, Inc. All Rights Reserved Code Conversion Steps A ten-step guide to design conversion Step 1: Convert memories (using the Core Generator tool) Step 2: Convert DCMs and PLLs (using the Architecture Wizard) Step 3: Convert SERDES (using the ChipSync Wizard) Step 4: Convert DSP (using the Core Generator tool) Step 5: Replace IP (using the Core Generator tool) Step 6: Use the Xilinx SRL (HDL) Step 7: Use clock enables (HDL) Step 8: Employ other good HDL coding styles (HDL) Step 9: Pipeline combinatorial logic (good design practice) Step 10: Build effective finite state machines (HDL)

13. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2009 Xilinx, Inc. All Rights Reserved Replace ASIC Memory Depth, width, and functionality will determine the type of memory to use Off-chip RAM Megabytes of memory storage Use SelectIO interfaces, DCM, and PLL for high-performance chip to chip Block SelectRAM™ memory 36 kb each—can be expanded for larger memories Configurable port aspect ratios Single-port, FIFOs, state machines, synchronous ROM FIFO Dedicated FIFO logic Distributed (LUT) RAM Synchronous write, asynchronous read Depth < 32 provides fastest performance One read and write port; one read-only port for dual-port RAMs

14. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2009 Xilinx, Inc. All Rights Reserved Off-Chip Memory Controllers for off-chip memory can be implemented in a Xilinx FPGA Use the Memory Interface Generator (MIG) The SelectIO technology resources allow for direct interaction with many different memory threshold levels HSTL or SSTL Several downloadable memory controllers available (VHDL and Verilog) from the Xilinx Memory Corner www.xilinx.com  Technology Solutions  Memory

15. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2009 Xilinx, Inc. All Rights Reserved Block SelectRAM Memory Use Simple dual-port and single-port synchronous RAMs can be inferred by Mentor, Synopsys, and XST Your coding style must include 1) Synchronous write 2) Registered read address 3) Requires synthesis attributes for inference of proper resources For advanced block RAM use, create the RAM with the CORE Generator tool Configurable aspect ratio, for example Port A – 512 x 8; Port B – 256 x 16 Port A – 1024 x 8; Port B – 1024 x 32

16. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2009 Xilinx, Inc. All Rights Reserved Block SelectRAM Memory Inference type blockram_512x8 is array (0 to 511) of std_logic_vector(7 downto 0); signal mem : blockram_512x8; signal addr_q : std_logic_vector (8 downto 0); begin process (clk) begin if rising_edge(clk) then addr_q <= addr; if we = '1' then mem(conv_integer(addr)) <= di; end if; end process; do <= mem(conv_integer(addr_q));

17. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2009 Xilinx, Inc. All Rights Reserved Block RAM Inference Notes Synthesis tools can only infer “simple” block RAMs, that is Single-port block RAMs with read and write on the same port Dual-port block RAMs with read and write on individual ports Synthesis tools cannot infer block RAMs with Configurable aspect ratios Ports with different widths With output enable and reset functionality Block RAMs with read and write capability on both ports Dual-port with different clocks on each port These limitations for inferring “advanced” block RAMs can be overcome by creating the RAM with the CORE Generator tool or instantiating primitives

18. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2009 Xilinx, Inc. All Rights Reserved Memory Interface Generator Generates a complete memory controller and interface design Output: RTL, UCF, documentation, and timing analysis VHDL or Verilog Choose from a predefined catalog of available devices and interfaces Checks SSO and all pin selection rules Available as part of the CORE Generator tool (free)

19. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2009 Xilinx, Inc. All Rights Reserved Distributed RAM Distributed memory resources can be correctly inferred by Synopsys, Mentor, and XST All distributed RAMs can be inferred Requires characterization of – 1) Synchronous write – 2) Asynchronous read Older Synopsys tools may infer combinatorial feedback loops How would you find out? Can also be created with the CORE Generator tool This is generally recommended

20. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2009 Xilinx, Inc. All Rights Reserved Distributed RAM Example reg [3:0] ram64x4 [0:63]; always @ (posedge clk) if (we) ram64x4[addr] <= din; assign dout = ram64x4[addr];

21. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2009 Xilinx, Inc. All Rights Reserved Distributed ROM ROM can be inferred by Mentor, Synopsys, and XST In VHDL, create an array of constants In Verilog, use a case statement with the address as the selector expression and assign constant values at those addresses

22. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2009 Xilinx, Inc. All Rights Reserved Distributed ROM Example type rom4x2 is array (0 to 3) of std_logic_vector (1 downto 0); constant rom : rom4x2 := ("00", "11", "01", "10"); begin dout <= rom(conv_integer(addr));

24. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2009 Xilinx, Inc. All Rights Reserved Digital Clock Manager and PLL The DCM provides powerful clock management features DLL is used to eliminate clock skew DFS is used to provide a wide range of clock synthesis DPS is used for fine-grain phase shifting The PLL provides frequency synthesis and jitter filter Replace an ASIC PLL with a Xilinx PLL (or a DCM) Be aware of the DCM limitations by referring to your FPGA’s data sheet or user guide

25. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2009 Xilinx, Inc. All Rights Reserved DCM Instantiation Instantiate the DCM primitive, IBUFG clock input primitive, and BUFG global clock buffer primitive IBUFG Assigns input signal to a dedicated clock pin BUFG Gets the chosen clock on a global buffer

26. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2009 Xilinx, Inc. All Rights Reserved InClk 1 To Global Clocks CMT DCM PLL Filter DCM output clock jitter InClk 1 To Global Clocks CMT DCM PLL Filter high clock jitter before reaching the DCM InClk 1 InClk 2 InClk 3 To Global Clocks DCM PLL CMT DCM Use each DCM and PLL individually Standard CMT Configurations

27. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 27 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 27 © 2009 Xilinx, Inc. All Rights Reserved Three Types of Clock Resources Performance matched to application needs 710-MHz I/O Clocks 710-MHz I/O Clocks 550-MHz Global Clocks 550-MHz Global Clocks 300-MHz Regional Clocks 300-MHz Regional Clocks Performance matched to application needs 710-MHz I/O Clocks 710-MHz I/O Clocks 550-MHz Global Clocks 550-MHz Global Clocks 300-MHz Regional Clocks 300-MHz Regional Clocks Global Muxes Global clocks Regional clocks I/O clocks I/O Column Clock region height: 20 CLBs 40 I/Os (1 bank) Clock region width: One half the chip 8–24 clock regions per device Clock region height: 20 CLBs 40 I/Os (1 bank) Clock region width: One half the chip 8–24 clock regions per device

28. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 28 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 28 © 2009 Xilinx, Inc. All Rights Reserved Virtex-5 FPGA I/O Clocking Clock-Capable I/O I/O Clock Buffer (BUFIO) I/O Clock Net (IOCLK) Per region: Four clock-capable I/Os Four I/O clock buffers Four I/O clock nets BUFIOs cannot drive IOCLK track in adjacent region Per region: Four clock-capable I/Os Four I/O clock buffers Four I/O clock nets BUFIOs cannot drive IOCLK track in adjacent region I/O Column Ideal for source- synchronous interfaces

29. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 29 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 29 © 2009 Xilinx, Inc. All Rights Reserved Virtex-5 FPGA Regional Clocking Clock-capable I/O Regional Clock Buffer (BUFR) Regional Clock Net (RCLK) Per region: Four clock-capable I/Os Two regional clock buffers Four regional clock nets Per region: Four clock-capable I/Os Two regional clock buffers Four regional clock nets 4 2 4 4 2 2 2 2 2 2 Easily create many clock domains per FPGA

30. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 30 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 30 © 2009 Xilinx, Inc. All Rights Reserved Architecture Wizard Double-click Create New Source Select IP (CORE Generator & Architecture Wizard) and click Next

31. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 31 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 31 © 2009 Xilinx, Inc. All Rights Reserved Clocking Wizard Choose function Optimal DCM/PLL flow automatically selected Choose function Optimal DCM/PLL flow automatically selected Choose component Program as desired Choose component Program as desired - or -

32. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 32 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 32 © 2009 Xilinx, Inc. All Rights Reserved Customize the DCM Main window Select pins Specify Reference source Clock frequency Phase shift Advanced button Wizard generates ready-to-use VHDL or Verilog wrappers and components Use the GUI to instantiate and program your clocking components Xilinx Clocking Wizard

34. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 34 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 34 © 2009 Xilinx, Inc. All Rights Reserved SelectIO Technology Instantiate SERDES resources with the Memory Interface Generator (MIG) or by direct instantiation of resources customized with the ChipSync Wizard Instantiate SelectIO interface buffers to connect directly to over 40 different I/O standards Eliminates threshold translators; therefore decreasing delay and board area Synthesis tools allow the SelectIO interfaces to be specified in their constraint tools or through code attributes Single-ended and differential I/O standards can also be selected in PinAhead or set in a UCF

35. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 35 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 35 © 2009 Xilinx, Inc. All Rights Reserved PinAhead Pin Assignment analysis Tool includes a DRC check and WASSO analysis Allows you to see both a Package and Pin view of your design Makes it easy to make pin assignments and attributes I/O Ports View Package Pins View Properties, Selection Views Clock Regions View Package View Device View

36. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 36 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 36 © 2009 Xilinx, Inc. All Rights Reserved Source-Synchronous Memory ChipSync technology Programmable IDELAY and ODELAY Integrated I/O SERDES Fast regional and I/O clocks Embedded ECC logic Reduces logic resources Increases performance Proven memory interfaces DDR-II DRAM and QDR/QDR-II, for example XCITE: Internal impedance control Virtex™-5 FPGA Data Forwarded CLK/DQS SelectIO™ interface ChipSync technology

37. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 37 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 37 © 2009 Xilinx, Inc. All Rights Reserved Frequency division Data width to 10 bits Dynamic signal alignment Bit alignment Word alignment Clock alignment Supports Dynamic Phase Alignment (DPA) ChipSync™ n ISERDES CLK CLKDIV FPGA Fabric BUFIO BUFR ÷ ÷ CLK Data ISERDES

38. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 38 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 38 © 2009 Xilinx, Inc. All Rights Reserved OSERDES ChipSync™ChipSync™ n CLKCLKDIV m FPGA Fabric BUFIO/BUFR DCM/PMCD BUFIO/BUFR DCM/PMCD Two separate SERDES included Data SERDES: 2, 3, 4, 5, 6, 7, 8, 10 bits Three-state SERDES: 1, 2, 4 bits Ideal for memories

39. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 39 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 39 © 2009 Xilinx, Inc. All Rights Reserved ChipSync Wizard Generates a complete SERDES interface Provides a VHDL or Verilog instantiation plus a Xilinx netlist (.xaw file extension) Choose from a list of supported I/O standards and SERDES programmability Available as part of the CORE Generator tool (free)

40. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 40 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 40 © 2009 Xilinx, Inc. All Rights Reserved To obtain the desired performance and area goals, the design needs to be optimized for Xilinx FPGA flexibility This will require instantiating the appropriate resources with the appropriate tool Each synthesis tool requires different resources to be instantiated Know the limitations of your synthesis tools ability to infer resources We started the ten-step guide to design conversion Step 1: Convert memories (using the CORE Generator tool or MIG) Step 2: Convert DCMs and PLLs (using the Architecture Wizard) Step 3: Convert SERDES (using the ChipSync Wizard) Summary

41. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 41 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 41 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More? Xilinx online documents www.support.xilinx.com Software manuals – Synthesis and Simulation Design Guide » Includes general recommendations for coding practices and coding tips for specific FPGA families Virtex-5 FPGA User guide (SERDES, clocking resources) Xilinx Training www.xilinx.com/training Xilinx tools and architecture courses Hardware description language courses Basic FPGA architecture (free training videos)

42. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 42 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 42 © 2009 Xilinx, Inc. All Rights Reserved End of Part 1 You have completed ASIC to FPGA Coding Conversion, Part 1. The next course in the ASIC curriculum sequence is ASIC to FPGA Coding Conversion, Part 2 Comment Easy and quick. Please tell us what you think about this training. Continue More FPGA Courses Recorded e-Learning Next Course in the Sequence

43. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 43 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 43 © 2009 Xilinx, Inc. All Rights Reserved Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Trademark Information