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Last Year’s Mission Accomplished
0.2 0.4 0.6 0.8 1 1.2 Process Leadership Density Leadership Performance Leadership Price & Value Leadership Software Leadership Feature Size (micron) 5v 3.3v 2.5v 1.8v 1.3v 1990 1992 1994 1996 1998 2000 2002
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Transistor Count (millions)
Process Leadership Virtex 1 Million Gate 7.5 25 50 75 0.25u Process XC40250XV XC40150XV Transistor Count (millions) “samples today” XC40125XV 2Q98 4Q97 3Q98 4Q98 1Q98
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10 Million System Gates in 2002!
Density Leadership 10M Gates In 2002 10M 2M 1M 250k 180k 500k Virtex II Density (system gates) Virtex XC40250XV XC40125XV XC4085XL 10 Million System Gates in 2002!
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Architecture Innovation Leadership
Reconfigurable Logic On-Chip A/D-D/A Embedded Functions 1GHz Diff. Interface Built-in Logic Analyzer 133 MHz Block Dual Port RAM System I/O (LVTTL, SSTL, GTL) Vector Based Interconnect Phase Locked Loops 66 MHz 64-Bit PCI Features Distributed Dual Port RAM I/O Registers Internal Bussing 5V Tolerant I/O 3.3V and 5V PCI
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Performance Leadership Enabling high performance solutions first
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 PC 100 SDRAM Compliant 100 MHz DSP for Wireless Base Station 33 MHz PCI 2002 System Standards 233 MHz uP 300 MHz RAM I/F System Clock Rate* (MHz) 133 MHz SDRAM I/F 155 MHz SONET 66 MHz PCI 1995 1996 1997 1998 1999 2000 2001 2002 * 1/(Tsetup+Tclock-to-out)
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Packaging Leadership Flip Chip Technology Chip Scale Fine Pitch BGA
Pins Flip Chip Technology 1000 Chip Scale Fine Pitch BGA 700 SBGA <0.8mm 1.0mm BGA 500 HQFP 1.27mm PQFP 300 PGA PLCC 100
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CPLD Price Leadership Without Compromises Flexible ISP tPD = 4ns
Best Pin-Locking Industry Standard JTAG $15 XC95216/XL Price $7 $1.80 XC9536/XL $0.80 2001 2000 1999 1998 2002 * Prices are based on 100Ku+, slowest speed grade, lowest cost package
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Software Leadership Team Based Design Modular Guide Modular Compile
HDL- Centric Flows Largest Installed Base Highest Circuit Performance with M1 Fastest Timing Driven Compile Times Shrink-Wrapped FPGA Express Best flows & QOR with leading EDA vendors Push Button Design
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Compile Time Leadership
100 90 80 Up to 2.1X faster than 1.5 70 60 Minutes* 50 40 30 20 10 Release 1.4 1.5 2.1 2.2 * 100k System gate designs (200MHz Pentium) And with ... Faster CPUs Faster Compile Times Modular Compile 1999 Goal: 1 Million Gates in 45 minutes!
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Simple & Fast Low Cost CPLD Solutions
Variances In Interfaces SDRAM (i.e. Bank vs. SIMM) Unique System Back-End Isolates User From Interface Issues Critical Signal Timing Electrical Interfacing Control Signal Sequencing (State Machine Design)
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Flexible High Density FPGA Solutions JPEG Compression (70k ASIC Gates + RAM)
High Performance 2x NTSC Video Resolution 1.5x NTSC Pixel Depth FPGA Advantages over Chipsets Can specify Non-Standard Data-Rate & Pixel Depth Industrial Temp Range
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Real Technology Partnerships
Xilinx Delivers Committed to Product Leadership Focused on Complete Solutions Driving New Applications With Cores Delivering the Vision Real Technology Partnerships
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Introduction to Xilinx
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PLD Industry Growth
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Programmable Logic vs. Semi-Custom ASIC Market
Total 1996 Market – $9.5B Total 2001 Market – $15.8B Mask Programmed Gate Arrays $7.4B Mask Programmed Gate Arrays $5.6B 47% 59% 21% 20% 16% 37% Standard Logic $2.0B Programmable Logic Share $1.9B Standard Logic $2.6B Programmable Logic Share $5.8B Source: Dataquest, May 1997
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Foundation and Alliance Series
Who is Xilinx? World’s leading innovator of complete programmable logic solutions Inventor of the Field Programmable Gate Array $650M Annual Revenues; 35+% annual growth Fabless* Semiconductor and Software Company UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996} Yamaha (Japan) Seiko Epson (Japan) Programmable Logic Chips Foundation and Alliance Series Design Software
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Company Milestones 1984 Xilinx Founded
1985 Introduced first field programmable gate array (FPGA) 1987 Introduced second family of FPGAs 1988 Established subsidiary in Japan 1989 More than one million devices sold 1990 Initial public offering 1991 Introduced third family of FPGAs 1992 Expanded into complex programmable logic (CPLDs) 1993 Established Xilinx Hong Kong 1995 Xilinx ranked 10th largest ASIC supplier; Xilinx Ireland opens 1996 Xilinx ranked 8th largest ASIC supplier 1997 Industry’s first advanced 0.35 & 0.25 micron FPGAs 1998 Introduced low-cost Spartan FPGAs with RAM & cores 1998 Industry’s first provide system solution FPGA with Virtex
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Why Xilinx? Silicon Software Service Process Technology
Largest, fastest, lowest power FPGAs Lowest cost CPLDs Software Alliance Series: HDL, synthesis, EDA integration, optimization Foundation Series: ready to use, complete solutions LogiCORES & AllianceCORES: optimized and supported Service Most comprehensive field and on-line technical support Advanced Internet Web solutions Process Technology Deep submicron capacity — Sampling 0.22 micron now Better price, performance, density
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Military, High Reliability
Who’s Using Xilinx Industrial & Instrumentation Networking Military, High Reliability 12% 16% 4% 1% Misc 32% 35% Data Processing Communications Source: Xilinx
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How Customers Use Programmable Logic
Xilinx Provides Standard Parts “Blank” Integrated Circuits Customers Create Custom Circuits with Xilinx Software Tools When Design Is Final, Customers Go into Immediate Production
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Introduction to Programmable Logic Device Solution
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Programmable Logic Families
Source: Dataquest Logic Standard Logic ASIC Programmable Logic Devices (PLDs) Gate Arrays Cell-Based ICs Full Custom ICs SPLDs (PALs) CPLDs FPGAs Common Resources Configurable Logic Blocks (CLB) Memory Look-Up Table AND-OR planes Simple gates Input / Output Blocks (IOB) In/Out, latches, inverters, pullup/downs Interconnect or Routing Local, internal feedback, and global Acronyms SPLD = Simple Prog. Logic Device PAL = Prog. Array of Logic CPLD = Complex PLD FPGA = Field Prog. Gate Array
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CPLD and FPGA CPLD FPGA Complex Programmable Logic Device Field-Programmable Gate Array Architecture PAL/22V10-like Gate array-like More Combinational More Registers + RAM Basic Cell Product Term CLB & LUT Density Low-to-medium Medium-to-high 0.5-10K logic gates 1K to 1M system gates Application Combination based Register Based Timing Delay Predictable timing Application dependent Performance Predictable timing Application dependent Up to 250 MHz today Up to 150MHz today Interconnect “Crossbar Switch” Incremental
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FPGAs and CPLDs Often Co-Exist in the Same System
FPGAs excel at: higher density pipelined logic FIFOs, register files using RAM CPLDs excel at: deterministic performance fast pin-to-pin speed state machines wide decoding
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Why Programmable Logic ?
Faster Time to Market Immediate Prototypes Faster Debug Lower Risk PCB Development Faster Access to Hardware for Firmware/Software Development Test Marketing Capability Field Upgrade Potential Solve Gate Array Obsolescence Problems 5
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What’s Going on Xilinx Deep submicron arrived unexpectedly early
0.5µ-0.35µ-0.25µ-0.18µ-? Deep submicron technology provides “for free” speed, density, low cost But it requires voltage migration 5 V V V V V - ?
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Design Alternatives Microprocessors Gates, MSI, PALs
Ideal, if fast enough Gates, MSI, PALs Outdated, inefficient inflexible Dedicated Standard Chip Sets Cheap, but no product differentiation ASICs Only for rock-stable, high-volume designs Programmable Logic For flexibility and performance
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ASICs become less attractive
Non-recurring engineering cost increases more masking steps, more expensive masks Minimum order quantity rises larger wafers, smaller die Silicon capability exceeds user equirements Suppliers are leaving this overly competitive market
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FPGAs Are Gaining Acceptance
100 > 20x Bigger > 5x Faster > 50x Cheaper Capacity Speed Price 10 1 1/91 1/92 1/93 1/94 1/95 1/96 1/97 1/98 1/99 Year
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FPGAs Are Good Enough Adequate capacity, performance, price
200,000 gates, 85 MHz in 1998 1,000,000 gates, 200 MHz in 1999 Standard product advantages steep learning curve, cost decline performance gain, speed binning IC manufacturing is best at mass-production custom devices have an inherent disadvantage
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FPGAs are Good Enough Better
Deep submicron ASIC design is difficult second-order effects burden the traditional logic abstraction system designer needs help from EE Verification is very time consuming Hardware/software integration is delayed until a working chip is delivered.
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FPGAs Are Better User can focus on logic, not circuits
Xilinx solves all circuit problems clock delay and skew interconnect delay crosstalk I/O standards FPGAs are 100% tested by generic test methods Easy verification, incremental design Early hardware/software integration
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FPGAs Are Better Vastly Superior
Avoid the ASIC re-spin cost design error or market change Avoid the ASIC inventory risk over- or under-inventory obsolescence Reprogrammability last-minute design modifications last-step system customization field hardware upgrades reconfiguration per application reconfiguration per task ASICs will never offer these features
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CPLDs Complement FPGAs
CPLD strengths Wide address decoding Synchronous state machines Short combinatorial pin-to-pin delays Ideal for glue logic Low-cost Single-chip Non-volatile In-System Programmable Quick and easy to use
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Simple, Low-cost Solutions
Xilinx offers low-cost CPLD and FPGA devices and a low-cost Foundation software package The devices are fast and have systems-oriented features The software is powerful and easy to use. You need not be rich or a genius to use our programmable logic
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You can achieve reliable and predictable performance – automatically
100+MHz System Solutions The Virtex family provides efficient solutions for: Electrical and thermal issues I/O, logic, and memory design Alliance software provides powerful tools for a variety of design styles You can achieve reliable and predictable performance – automatically
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Three new Xilinx families
SpartanXL 3.3-V low-cost FPGA 5,000 to 40,000 gates XC9500XL 3.3-V In-System Programmable CPLD up to 200 MHz Virtex next-generation FPGA with system features up to a million gates
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More Xilinx Families XC3000A, XC3100A XC4000E, ’EX, ’XL, ’XLA, ’XV
for existing designs XC4000E, ’EX, ’XL, ’XLA, ’XV the industry’s most successful FPGAs XC5200 XC1700 Serial configuration PROMs for all families
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Xilinx FPGA Architecture Story
1997 11,000 Logic Cells (125k gates) fastest RAM 5 volt tolerant IOs buffered quad line VersaRing IOs 6ns pin-to-pin efficient segmented routing lowest power 1998 32,000 Logic Cells (400k gates) programmable IOs Advanced Clocking 100MHz system speed fast re-configure hierarchical memory solution 2000 65,000 Logic Cells (800k gates) built-in logic analyzer D/A & A/D support custom cores high speed differential interface (500MHz)
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Ram Base Reconfigurable Logic
Advantages Testability, incremental design, fast redesign Experimentation with novel architectures Easy upgrade or design modifications in production / field Applications Multi-purpose hardware - one card for several applications: Video formats, telecom standards, bus protocols, Intel vs Motorola CPU, printer resolution, ... Time-shared hardware Diagnostics, instrumentation
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Xilinx FPGA Architecture
High Density -> 1M System Gates SRAM Based LUT for Synchronous Dual Port RAM or Logic ASIC-like array structure Built-in Tri-States Infinite reconfigurations, downloaded from PC or workstation in ~1 second Configurable Logic Blocks (CLBs) I/O Blocks (IOBs) Programmable Interconnect
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Logic in FPGAs Logic is implemented in Look-up-Tables - not gates
Architecture is very rich in Flip-Flops IOB CLB LUT F/Fs IOB CLB LUT F/Fs IOB IOB IOB CLB LUT F/Fs IOB IOB IOB Clock
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I/O Block (IOB) Identical I/O Blocks line the periphery of die
Input, output, or bi-directional Registered, latched, or combinatorial Three-state output Programmable output slew rate
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CLB (Configurable Logic Block)
2 4-input LUTs and 1 3-input LUT ” muxes feed F/G LUTs or independent inputs to H LUT 2 edge-triggered FFs DIN EC SR 4 outputs Fed by “B” muxes
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Programmable Interconnect
Resources to create arbitrary interconnection networks Hierarchy of interconnect resources direct local long-line global Connections are made by the use of programmable switches CLB CLB Switch Matrix CLB CLB
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What’s CPLD Architecture
Similar to having multiple PAL devices inter connected in one chip Best applications Wide functions Fast arithmetic Complex counters Complex state machines PAL/GAL or TTL integration Non-volatile PAL Swi- tch Mat- rix PAL PAL PAL Prog. AND array Fixed OR array FF/ Macro- cell FF/ Macro- cell
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Why FLASH Technology? Product benefits due to 67% smaller FLASH cell
FastFLASH Cell Typical E2 CPLD Cell S1 3X Routing Switches Source S2 Data S1 S3 Control Word Line Product benefits due to 67% smaller FLASH cell More routing switches in the same area supports pinlocking Lower parasitic capacitance improves performance Long term cost improvements due to scalability Greatly improved endurance with FLASH Lower program/erase voltages
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Flash vs E2 Endurance Flash delivers: -highest quality
-no speed degradation -20 year retention -reliable reprogramming -worry free field upgrade
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ISP Market Growth
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Functions of 5 Product Term are fastest
Xilinx CPLDs use a Sum of Products Architecture From 5 P-terms to 15 P-terms cost under 1ns of tpd AND functions are “free”, Ors are not. An OR gate equals a Macrocell Inverters are free 36/54 Input 5 Product Term
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Naming Conventions Xilinx Component naming convention: Part name -speed -package. Example: XC4028XL-3-BG256C Operation condition (C:Com, I:Indst, M:Mil) Package Speed Grade Sub-family (3V = XL, no XL = 5V) Maximum number of gates (thousands) Family (4000, 9500 …) Spartan names start with XCS The speed grade is a relative measure of internal delay. Smaller numbers mean faster parts for all families EXCEPT Spartan. For Spartan, larger numbers mean faster parts.
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