1. Lecture 2 VHDL: Introduction Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University

2. Outline History Design units: Event-driven simulation Signal Assignments: A. Simple B. Conditional C. Selected

3. History VHDL: VHSIC Hardware Description Language VHSIC: Very High Speed Integrated Circuit VHDL is sponsored by Dept. of Defense (USA) First IEEE standard: IEEE 1076-1987. (VHDL’87) Second IEEE standard: IEEE 1076-1993. (VHDL’93) Commercial simulation and synthesis tools based on IEEE 1076-1993 is available in 1996 IEEE 1076.3 1076.4 (VITAL) 1997 (VHDL Initialtive Towards ASIC Libraries) VHDL-AMS (analog mixed signal) 1997

4. VHDL vs. Verilog USA-IBM, TI, AT&T, INTEL, ….. VHDL USA-Silicon Valley……………… Verilog Europe……………………………. VHDL Japan …………………………….. Verilog Korea …………………………….. VHDL(~75%) Taiwan …………………………… VHDL(~50%)

5. VHDL Hardware Design Cycle System Modeling System Modeling RTL Design RTL Design Synthesis Requirement Specification Design Implementation VHDL

6. VHDL Hardware Design Cycle System modeling: A. Specify at a system level what is to be achieved by the circuit. B. use VHDL to create a simulation model C. the model can be run on simulator to check the functionality D. No hardware implementation (pure algorithm) E. System-level model can be used to confirm with a customer that their design requirement have been understood.

7. VHDL Hardware Design Cycle RTL Design: A. system model is transformed into a register-transfer level (RTL) design B. RTL is inherently a synchronous design methodology C. Timing: Clock cycle D. Circuit: Block level

8. VHDL Hardware Design Cycle E. Basic design steps: 1. Identify the data operations. 2. Determine the precision of the operations 3. Decide what data processing resources to provide. 4. Allocate operations to resources. 5. Allocate registers for intermediate results. 6. Design the controller 7. Design the reset mechanism. F. VHDL model of RTL design can be simulated and checked against the system design

9. VHDL Hardware Design Cycle Logic Synthesis: A. RTL design is synthesized into gate level (netlist) B. the resulting gate-level netlist or schematic can be simulated against the RTL design to confirm that the synthesized circuit behaves in the same way. C. Meet Timing requirement and Area constraints D. The netlist is supplied to the “placement and routing“ tools for circuit layout (FPGA or VLSI Chip)

10. Example Circuit: cross product (System model) package cross_product_types is type int_vector is array(0 to 7) of integer; end; use work.cross_product_types.all; entity cross_product is port (a, b: in int_vector; z: out integer); end; architecture system of cross_product is begin proces(a,b) variable z_var: integer; begin z_var :=0; for I in 0 to 7 loop z_var := z_var + a(I) * b(I); end loop; z <= z_var; end process; end;

11. 8 multipliers 7 adders Area: 40000 NAND gates I/O: 546 ports

12. RTL Design: 1. Identify the data operations. Data operations: multiplications and additions Eight two-input multiplications and one eight-input addition 8-input addition => balanced tree adder => skewed tree adder Which implementation is better? Fig 2.3 skewed tree adders:

13. RTL Design: 2. Determine the precision of the operations Overflow during additions (Is it possible?) Data (operand) precision(Do we know in advance?) If Data inputs are 8-bit 2’s complement then what precision for the other datapath? Ans: 16-bit 2’s complement

14. RTL Design: 3. Decide what data processing resources to provide. How may multipliers and adders are required to implement the cross-product algorithm? One-to-one mapping of operations to hardware resources: 8 multipliers and 7 adders Design constraints: performance, power, cost Low cost implementation: one 8-bit (16-bit result) multiplier and one 16-bit adder

15. RTL Design: 4. Allocate operations to resources. This step is commonly referred to as “allocation and scheduling” Allocation: mapping data operations onto hardware resources. Scheduling: which operations will be preformed in which clock cycle. See Table 2.1 (pp. 12). Cross-product circuit see (Fig 2.4 in next page).

16. RTL Desing: 5. Allocate registers for intermediate results. Only one (16-bit) register is required Datapath of Cross product

17. RTL Design: 6. Design the controller Design the controller to sequence the operations over the eight clock cycles See Fig 2.4 in previous page. three multiplexers and one register We need control path (controller) to control the the datapath. (See table 2.2 and Fig 2.5) Controll path of Cross product

18. RTL Design: 7. Design the reset mechanism. Reset mechanism: power on and reset will put the system in known state. In this example the datapath will be cleared by the design of the controller.

19. Library ieee; Use ieee.std_logic_1164.all, ieee.numeric_std.all; package cross_product_types is subtype sig8 is signed(7 downto 0); type sig8_vector is array(natural range <>) of sig8; end; Library ieee; Use ieee.std_logic_1164.all, ieee.numeric_std.all; use work.cross_product_types.all; entity cross_product is port (a, b: in sig8_vector(7 downto 0); ck, reset: in bit; result: out signed(15 downto 0)); end;

20. a_mux: ai <= a(i); b_mux: bi <= b(i); multiply: product <= ai*bi; z_mux: add_in <= X”0000” when I = 0 else accumulator; add: sum <= product + add_in; accumulator: proces(ck) begin if ck’event and ck = ‘1’ then accumulator <= sum; end if; end process; output: result <= accumulator; end;

21. Synthesis Results SystemRTLmodel ====================================== A. NAND Equivalent 400001200 B. Port 546146 C. Clock Cycle-8 D. Registers019 ======================================

22. VHDL: five design units Design Units: basic building blocks of VHDL. Five design Units: A. entity: Primary unit B. architecture: Secondary unit C. package: Primary unit D. package body: Secondary unit E. configuration declaration: Primary unit A VHDL file may contain any number of design units Primary design unit can exist on its own. Secondary design unit can not exist without its corresponding primary unit.

23. VHDL: Design Units entity: a primary design unit that defines the interface of a circuit architecture: a secondary design unit that define the contents of the circuit entity NAND2 is port (A,B: in std_logic; Z: out std_logic ); end nand2; NAND2 A B Z architecture behavior of NAND2 is begin Z <= A nand B; end;

24. More architecture architecture structure of NAND2 is signal I: std_logic; begin comp1: an02d1 port map(A,B,I); comp2: in01d1 port map(I, Z); end; architecture RTL of NAND2 is begin process(A,B) if (A=‘1’) and (B=‘1’) then Z<=‘1’; else Z<=‘0’; end process; end;

25. configuration configuration useWhichImplementation of NAND2 is for RTL end for; end; configuration: a primary design unit to define which hierarchical design is to be used. No corresponding secondary design unit.

26. Simulation model VHDL simulator: an event-driven simulator. Three essential concepts: A. simulation time B. delta time C. event processing Simulation cycle: event processing and process execution

27. RS Latch process(R,S) begin Q <= R nor Qbar; Qbar <= S nor Q; end process; S R Q Q’ P1: process(R,Qbar) begin Q <= R nor Qbar; end process; P2: process(S,Q) begin Qbar <= S nor Q; end process;

28. Simulation: Initial: Q=‘1’ and Qbar=‘0’ ( R=S=‘0’) R is set to ‘1’ (a transaction in event-driven simulation) delta 1: event processing the transaction make R active and it causes an event on R(‘0’=>’1’). This event triggers process P1. delta 1: process execution P1 recalculates the value of Q (‘1’=>’0’) and the transaction is added to transaction queue. delta 2:...

29. Signals and Ports Signals are the carries of data values around an architecture. Port are the same as signal but also provide an interface through the entity so that the entity can be used as a subcircuit in a hierarchical design, A signal is declared in the declarative part of an architecture architecture structure of adder is signal a,b,c: bit; begin …. end;

30. architecture structure of adder is signal a: bit; signal b: bit; signal c: bit; begin …. end;

31. Signals and Ports Port declarations are enclosed by a port specificaiton in the entity entity adder is port (a,b,c: in bit); end; First part: a list of port names (a,b,c). Second part: mode of the port (in) third part: type of the port (bit)

32. I/O directin in: input port out: output port inout: bidirectional port buffer: output port (may not synthesizable)

33. Basic Data Type bit: 0, 1 bit_vector (0 to 7) std_logic: 0,1, U, Z, H, L, X, std_logic_vector (15 downto 0)

34. initial values All signals have an initial value when simulation begins. Initial value can be user-supplied in the signal declaration or given by default. Initial value given in signal declaration: signal a: bit :=‘1’; default value of a signal is the first (left) value. Bit (‘0’, ‘1’) For synthesis, there is no hardware interpretation of initial value. Designer’s responsibility to set circuits in known states

35. Signal Assignment: simple simple signal assignment: Format: target <= expr Example: x<=a xor b; Hardware mapping: xor a b c

36. Signal Assignment: conditional conditional signal assignment: Format: target <= { expr when expr else } expr Example: sum<=a xor b when c=‘1’ else not(a xor b) ; All the source expressions must be the same type as target of the assignment Hardware mapping: multiplexer

37. Signal Assignment: conditional The last branch of conditional signal assignment must be unconditional else. Multi-branch conditional signal assignment: z <= a when sel1=‘1’ else b when sel2=‘1’ else c ; Hardware mapping: a series of two-way multiplexers

38. Signal Assignment: conditional Redundant branch conditional signal assignment: z <= a when sel=‘1’ else b when sel=‘0’ else c ; Hardware mapping: a series of two-way multiplexers Optimization (maybe)

39. Signal Assignment: selected Selected signal assignment: Format: with expr select target <= { expr when choices, } expr when choices; Example: with sel select z <= a when ‘1’, b when ‘0’;

40. Example: 8-bit parity checker entity parity is port (d7, d6, d5, d4,d3, d2,d1, d0: in bit; mode: in bit; result: out bit); end; architecture behavior of parity is signal sum:bit; begin sum <=d0 xor d1 xor … d6 xor d7 result <=sum when mode=‘1’ else not sum; end