1. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Static CMOS Logic ECE442: Digital Electronics

2. Spring 2008, CSUN, Zahid CMOS Circuit Styles  Static complementary CMOS - except during switching, output connected to either V DD or GND via a low-resistance path l high noise margins -full rail to rail swing -V OH and V OL are at V DD and GND, respectively l low output impedance, high input impedance l no steady state path between V DD and GND (no static power consumption) l delay a function of load capacitance and transistor resistance l comparable rise and fall times (under the appropriate transistor sizing conditions)  Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes l simpler, faster gates l increased sensitivity to noise

3. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Static Complementary CMOS V DD F(In 1,In 2,…In N ) In 1 In 2 In N In 1 In 2 In N PUN PDN PUN and PDN are dual logic networks … …  Pull-up network (PUN) and pull-down network (PDN) PMOS transistors only pull-up: make a connection from V DD to F when F(In 1,In 2,…In N ) = 1 NMOS transistors only pull-down: make a connection from F to GND when F(In 1,In 2,…In N ) = 0

4. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Threshold Drops V DD V DD  0 PDN 0  V DD CLCL CLCL PUN V DD 0  V DD - V Tn CLCL V DD V DD  |V Tp | CLCL S DS D V GS S SD D

5. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Construction of PDN  NMOS devices in series implement a NAND function  NMOS devices in parallel implement a NOR function A B A B AB A + B

6. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Dual PUN and PDN  PUN and PDN are dual networks l DeMorgan’s theorems A + B = A B [!(A + B) = !A !B or !(A | B) = !A & !B] A B = A + B [!(A B) = !A + !B or !(A & B) = !A | !B] l a parallel connection of transistors in the PUN corresponds to a series connection of the PDN  Complementary gate is naturally inverting (NAND, NOR, AOI, OAI)  Number of transistors for an N-input logic gate is 2N

7. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid CMOS NAND A B A B AB ABF 001 011 101 110 A B

8. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid CMOS NOR A + B A B ABF 001 010 100 110 AB A B

9. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Complex CMOS Gate OUT = (D + A (B + C))* D A BC

10. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Complex CMOS Gate OUT = (D + A (B + C))* D A BC D A B C

11. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Example: OAI Logic C AB X = (C (A + B))* B A C A B C

12. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Example: OAI Logic C AB X = ((A+B)(C+D))* B A D C D A B C D

13. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Example 1 of a Complex CMOS Gate

14. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Example 2 of a Complex CMOS Gate

15. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Example 3 of a Complex CMOS Gate

16. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid XNOR/XOR Implementation A B A  B A B XNORXOR A  B A B A B  How many transistors in each?

17. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid VTC is Data-Dependent A B F= A B AB M1M1 M2M2 M3M3 M4M4 Cint V GS1 = V B V GS2 = V A –V DS1 0.5  /0.25  NMOS 0.75  /0.25  PMOS  The threshold voltage of M 2 is higher than M 1 due to the body effect (  ) V Tn2 = V Tn0 +  (  (|2  F | + V int ) -  |2  F |) since V SB of M 2 is not zero (when V B = 0) due to the presence of Cint V Tn1 = V Tn0 D D S S weaker PUN

18. ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Static CMOS Full Adder Circuit B BB BB B B B A A A A A A A A C in !C out !Sum C* out = C* in & (A* | B*) | (!A & !B) C out = C in & (A | B) | (A & B) !Sum = C out & (!A | !B | !C in ) | (!A & !B & !C in ) Sum = !C out & (A | B | C in ) | (A & B & C in )