1. FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved Basic HDL Coding Techniques Part 1

2. Welcome If you are new to FPGA design, this module will help you build good HDL code that is optimized for an FPGA These design techniques promote fast and efficient FPGA designs

3. Specify FPGA resources that may need to be instantiated Identify some basic design guidelines that successful FPGA designers follow Select a proper HDL coding style for fast, efficient circuits After completing this module, you will able to:

4. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2009 Xilinx, Inc. All Rights Reserved Breakthrough Performance Three steps to achieve breakthrough performance 1. Utilize dedicated resources Dedicated resources are faster than a LUT/flip-flop implementation and consume less power Typically built with the CORE Generator tool and instantiated DSP48E, FIFO, block RAM, ISERDES, OSERDES, EMAC, and MGT, for example 2. Write code for performance Use synchronous design methodology Ensure the code is written optimally for critical paths Pipeline when necessary 3. Drive your synthesis tool Try different optimization techniques Add critical timing constraints in synthesis Preserve hierarchy Apply full and correct constraints Use High effort Performance Meter Virtex™-6 FPGA

5. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2009 Xilinx, Inc. All Rights Reserved Use Dedicated Blocks Dedicated block timing is correct by construction Not dependent on programmable routing Uses less power Offers as much as 3x the performance of soft implementations Examples Block RAM and FIFO at 600 MHz DSP48E at 600 MHz Phy Interface Rx Stats Mx Rx Stats Mx Tx Stats Mx Tx Stats Mx EMAC Core Host Interface Statistics Interface Client Interface Host Bus DCR Bus Proce ssor Interfa ce Proce ssor Interfa ce Smart RAM FIFO FIFO Dual-Port BRAM Dual-Port BRAM EMAC Core DSP48E Slice

6. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2009 Xilinx, Inc. All Rights Reserved Timing Closure

7. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2009 Xilinx, Inc. All Rights Reserved Instantiation versus Inference Instantiate a component when you must dictate exactly which resource is needed The synthesis tool is unable to infer the resource The synthesis tool fails to infer the resource Xilinx recommends inference whenever possible Inference makes your code more portable Xilinx recommends using the CORE Generator software to create functions such as Arithmetic Logic Units (ALUs), fast multipliers, and Finite Impulse Response (FIR) filters for instantiation Xilinx recommends using the Architecture Wizard utility to create DCM, PLL, and clock buffer instantiations

8. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2009 Xilinx, Inc. All Rights Reserved FPGA Resources Can be inferred by all synthesis tools Shift register LUT (SRL16E/ SRLC32E) F7 and F8 multiplexers Carry logic Multipliers and counters using the DSP48E Global clock buffers (BUFG) SelectIO™ (single-ended) interface I/O registers (single data rate) Input DDR registers Can be inferred by some synthesis tools Memories Global clock buffers (BUFGCE, BUFGMUX, BUFGDLL) Some DSP functions Cannot be inferred by any synthesis tools SelectIO (differential) interface Output DDR registers DCM / PLL Local clock buffers (BUFIO, BUFR)

9. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2009 Xilinx, Inc. All Rights Reserved Suggested Instantiation Xilinx recommends that you instantiate the following elements Memory resources Block RAMs specifically (use the CORE Generator software to build large memories) SelectIO interface resources Clocking resources DCM, PLL (use the Architecture Wizard) IBUFG, BUFGMUX_CTRL, BUFGCE BUFIO, BUFR

10. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2009 Xilinx, Inc. All Rights Reserved Why does Xilinx suggest this? Easier to port your HDL to other and newer technologies Fewer synthesis constraints and attributes to pass on Keeping most of the attributes and constraints in the Xilinx User Constraints File (UCF) keeps it simple—one file contains critical information Create a separate hierarchical block for instantiating these resources Above the top-level block, create a Xilinx “wrapper” with instantiations specific to Xilinx Instead use VHDL configuration statements or put wrappers around each instantiation This maintains hierarchy and makes it easy to swap instantiations Top-Level Block Top-Level Block BUFG DCM IBUFG Xilinx “wrapper” top_xlnx IBUFOBUF START UP Suggested Instantiation

11. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2009 Xilinx, Inc. All Rights Reserved Hierarchy Management Synplify and XST software The basic settings are Flatten the design: Allows total combinatorial optimization across all boundaries Maintain hierarchy: Preserves hierarchy without allowing optimization of combinatorial logic across boundaries (recommended) If you have followed the synchronous design guidelines, use the setting -maintain hierarchy If you have not followed the synchronous design guidelines, use the setting -flatten the design. Consider using the “keep” attribute to preserve nodes for testing Your synthesis tool may have additional settings Refer to your synthesis documentation for details on these settings

12. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2009 Xilinx, Inc. All Rights Reserved Hierarchy Preservation Benefits Easily locate problems in the code based on the hierarchical instance names contained within static timing analysis reports Enables floorplanning and incremental design flow The primary advantage of flattening is to optimize combinatorial logic across hierarchical boundaries If the outputs of leaf-level blocks are registered, there is generally no need to flatten

13. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2009 Xilinx, Inc. All Rights Reserved Multiplexers Multiplexers are generated from IF and CASE statements IF/THEN statements generate priority encoders Use a CASE statement to generate complex encoding There are several issues to consider with a multiplexer Delay and size Affected by the number of inputs and number of nested clauses to an IF/THEN or CASE statement Unintended latches or clock enables Generated when IF/THEN or CASE statements do not cover all conditions Review your synthesis tool warnings Check by looking at the component with a schematic viewer

14. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2009 Xilinx, Inc. All Rights Reserved IF/THEN Statement Priority Encoder Most critical input listed first Least critical input listed last do_c do_e cond_c cond_b do_b cond_a do_a crit_sig do_d oput 1 0 1 0 1 0 1 0 IF ( crit_sig ) THEN oput <= do_d ; ELSIF cond_a THEN oput <= do_a ; ELSIF cond_b THEN oput <= do_b; ELSIF cond_c THEN oput <= do_c; ELSE oput <= do_e ; END IF;

15. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2009 Xilinx, Inc. All Rights Reserved Avoid Nested IF and IF/ELSE Nested IF or IF/THEN/ELSE statements form priority encoders CASE statements do not have priority If nested IF statements are necessary, put critical input signals on the first IF statement The critical signal ends up in the last logic stage

16. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2009 Xilinx, Inc. All Rights Reserved CASE Statements CASE statements in a combinatorial process (VHDL) or always statement (Verilog) Latches are inferred if outputs are not defined in all branches Use default assignments before the CASE statement to prevent latches CASE statements in a sequential process (VHDL) or always statement (Verilog) Clock enables are inferred if outputs are not defined in all branches This is not “wrong”, but might generate a long clock enable equation Use default assignments before CASE statement to prevent clock enables

17. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2009 Xilinx, Inc. All Rights Reserved CASE Statements Register the select inputs if possible (pipelining) Can reduce the number of logic levels between flip-flops Consider using one-hot select inputs Eliminating the select decoding can improve performance Determine how your synthesis tool synthesizes the order of the select lines If there is a critical select input, this input should be included “last” in the logic for fastest performance

18. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2009 Xilinx, Inc. All Rights Reserved CASE Statement This Verilog code describes a 6:1 multiplexer with binary-encoded select inputs This uses fewer LUTs, but requires multiple LUTs in series on the timing critical path The advantage of using the “don’t care” for the default, is that the synthesizer will have more flexibility to create a smaller, faster circuit How could the code be changed to use one-hot select inputs? module case_binary (clock, sel, data_out, in_a, in_b, in_d, in_c, in_e, in_f) ; input clock ; input [2:0] sel ; input in_a, in_b, in_c, in_d, in_e, in_f ; output data_out ; reg data_out; always @(posedge clock) begin case (sel) 3'b000 : data_out <= in_a; 3'b001 : data_out <= in_b; 3'b010 : data_out <= in_c; 3'b011 : data_out <= in_d; 3'b100 : data_out <= in_e; 3'b101 : data_out <= in_f; default : data_out <= 1'bx; endcase end endmodule

19. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2009 Xilinx, Inc. All Rights Reserved CASE Statement This is the same code with one-hot select inputs This used more LUTs, but requires fewer logic levels on the timing critical path This yields a greater benefit when the mux is larger Enumerated types allow you to quickly test different encoding …and makes simulation more readable module case_onehot (clock, sel, data_out, in_a, in_b, in_d, in_c, in_e, in_f) ; input clock ; input [5:0] sel ; input in_a, in_b, in_c, in_d, in_e, in_f ; output data_out ; reg data_out; always @(posedge clock) begin case (sel) 6'b000001 : data_out <= in_a; 6'b000010 : data_out <= in_b; 6'b000100 : data_out <= in_c; 6'b0010 00: data_out <= in_d; 6'b010000 : data_out <= in_e; 6'b100000 : data_out <= in_f; default : data_out <= 1'bx; endcase end endmodule

20. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2009 Xilinx, Inc. All Rights Reserved Other Basic Performance Tips Avoid high-level loop constructs Synthesis tools may not produce optimal results Order and group arithmetic and logical functions and operators A <= B + C + D + E; should be: A <= (B + C) + (D + E) Use a synchronous reset More reliable system control

21. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2009 Xilinx, Inc. All Rights Reserved Synchronous Design Rewards Always make your design synchronous Recommended for all FPGAs Failure to use synchronous design can potentially Waste device resources Not using a synchronous element will not save silicon and it wastes money Waste performance Reduces capability of end products; higher speed grades cost more Lead to difficult design process Difficult timing specifications and tool-effort levels Cause long-term reliability issues Probability, race conditions, temperature, and process effects Synchronous designs have Few clocks Synchronous resets No gated clocks; instead, clock enables Ken Chapman (Xilinx UK) 2003

22. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2009 Xilinx, Inc. All Rights Reserved Inferred Register Examples always @(posedge CLOCK) Q = D_IN; always @(posedge CLOCK or posedge RESET) if (RESET) Q = 0; else Q = D_IN; always @(posedge CLOCK or posedge PRESET) if (PRESET) Q = 1; else Q = D_IN; always @(posedge CLOCK) if (RESET) Q = 0; else Q = D_IN; Ex 1 D Flip-Flop Ex 3. D Flip-Flop with Asynch Reset Ex 2. D Flip-Flop with Asynch Preset Ex 4. D Flip-Flop with Synch Reset

23. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2009 Xilinx, Inc. All Rights Reserved Clock Enables Coding style will determine if clock enables are used VHDL FF_AR_CE: process(ENABLE,CLK) begin if (CLK’event and CLK = ‘1’) then if (ENABLE = ‘1’) then Q <= D_IN; end if; end process Verilog always @(posedge CLOCK) if (ENABLE) Q = D_IN;

24. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2009 Xilinx, Inc. All Rights Reserved Summary Use as much of the dedicated hardware resources as possible to ensure optimum speed and device utilization Plan on instantiating clocking and memory resources Try to use the Core Generator tool to create optimized components that target dedicated FPGA resources (BRAM, DSP48E, and FIFO) Maintain your design hierarchy to make debugging, simulation, and report generation easier

25. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2009 Xilinx, Inc. All Rights Reserved Summary CASE and IF/THEN statements produce different types of multiplexers CASE statements tend to build logic in parallel while IF/THEN statements tend to build priority encoders Avoid nested CASE and IF/THEN statements You should always build a synchronous design for your FPGA Inferring many types of flip-flops from HDL code is possible Synchronous sets/resets are preferred

26. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More? Software Manuals Start  Xilinx ISE Design Suite 12.1  ISE Design Tools  Documentation  Software Manuals This includes the Synthesis & Simulation Design Guide This guide has example inferences of many architectural resources XST User Guide HDL language constructs and coding recommendations Software User Guides and software tutorials Xilinx Training www.xilinx.com/training Xilinx tools and architecture courses Hardware description language courses Basic FPGA architecture and other topics (free training videos!)

27. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 27 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 27 © 2009 Xilinx, Inc. All Rights Reserved Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Trademark Information