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Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.

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Presentation on theme: "Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1."— Presentation transcript:

1 Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1

2  Introduction  Algorithms  Experimental results  Conclusion 2

3 Technology Mapping(CutMap) Clustering(T-VPack) Placement(VPR:T-VPlace) Routing(VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 3

4 Technology Mapping(CutMap) Clustering(T-VPack) Placement(VPR:T-VPlace) Routing(VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 4

5 A B C D E mapping f2f2 f3f3 f1f1 A B C D E F Technology mapping transforms a netlist of gates and registers into a netlist of K-input lookup tables (K- LUTs) and registers.... f SRAM x y z... 0 0 1 0 1 5

6 Technology Mapping(CutMap) Clustering(T-VPack) Placement(VPR:T-VPlace) Routing(VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 6

7 Technology Mapping(CutMap) Clustering(T-VPack) Placement(VPR:T-VPlace) Routing(VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 7

8 Figure 1: An N cluster Figure 2: A LUT and flip-flop BLE 8

9 Technology Mapping(CutMap) Clustering(T-VPack) Placement(VPR:T-VPlace) Routing(VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 9

10 Technology Mapping(CutMap) Clustering(T-VPack) Placement(VPR:T-VPlace) Routing(VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 10

11 f3f3 f2f2 f1f1 A B C D E F f1f1 f2f2 f3f3 ABC D E F Mapping + Clustering Placement Routing 11

12 Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-T-VPlace) Routing(P-VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 12

13 Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-T-VPlace) Routing(P-VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 13

14 14

15 15

16 Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-T-VPlace) Routing(P-VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 16

17 Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-T-VPlace) Routing(P-VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 17

18  T-VPack  P-T-VPack Crit(B) is a measure of how close LUT B is to being on the critical path, Nets(B) is the set of nets connected to LUT B, Nets(C) is the set of nets connected to the LUTs already selected for cluster C Activity(i) is the estimated switching activity of net i, Activity avg is the average switching activity of all the nets in the user circuit. 18

19 19

20 Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-V-Place) Routing(P-VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 20

21 Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-T-VPlace) Routing(P-VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 21

22  T-Vplace  P-T-VPlace q(i) is used to scale the bounding boxes to better estimate wirelength for nets with more than 3 terminals, as described in [9]. Delay(i,j) is the estimated delay of the connection from source i to sink j, CE is a constant, and Criticality(i,j) is an indication of how close to the critical path the connection is [9]. bb x (i) and bb y (i) are the x and y dimensions of the bounding box of net i 22

23 23

24 Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-T-VPlace) Routing(P-VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 24

25 Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-T-VPlace) Routing(P-VPR Router) Circuit Delay / Area / Power Estimations FPGA CAD FLOWFPGA CAD FLOW FPGA CAD FLOWFPGA CAD FLOW 25

26  VPR-Router  P-VPR-Router The baseline VPR router uses the following cost function to evaluate a routing track n while forming a connection from source i to sink j: b(n) is the “base cost”, h(n) is the historical congestion cost, and p(n) is the present congestion of node n. Activity(i) is the switching activity in net i, MaxActivity is the maximum switching activity of all the nets, and MaxActCrit is the maximum activity criticality that any net can have. cap(n) is the capacitance associated with routing resource node n and ActCrit(i) is the activity criticality of net i. 26

27 27

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29  3-LUTs mappings: With duplicationNo duplication

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