1. CS294-6 Reconfigurable Computing Day 2 August 27, 1998 FPGA Introduction

2. Today: FPGA Basics Basic FPGA Composition XC4K, HSRA Designs to Bits

3. FPGA Field Programmable Gate Array Collection of programmable “gates” embedded in a flexible interconnect network. …a “user programmable” alternative to gate arrays.

4. Gates

5. Programmable Gate ?

6. Look-Up Table In Out 00 0 01 1 10 1 11 0 2-LUT

7. LUTs K-LUT -- K input lookup table Any function of K inputs by programming table

8. Conventional FPGA Tile K-LUT (typical k=4) w/ optional output Flip-Flop

9. Toronto FPGA Model

10. Toronto Model K input LUT Mesh interconnect C-box (connect LUT to interconnect) S-box switch interconnect

11. Typical Extensions Segmented Interconnect Hardwired/Cascade Inputs

12. Additional Assumption Single (SRAM) configuration bit for each: –LUT bit –interconnect point/option –flip-flop select

13. FPGA Basics LUT for compute FF for timing/retiming Switchable interconnect …everything we need to build fixed logic circuits –don’t really need programmable gates –latches can be built from gates

14. Admin. Breather Tools for homework

15. Commercial FPGA (XC4K) Cascaded 4 LUTs (2 4-LUTs -> 1 3-LUT) Fast Carry support Segmented interconnect Can use LUT config as memory.

16. XC4000 CLB

17. XC4K Interconnect

18. XC4K Interconnect Details

19. XC4K LUT Retiming

20. Hierarchical Synchronous, High- Speed Reconfigurable Array

21. HSRA 5-LUT with 5th input hardwired to neighbor –(can be used 4-input, 2-output LUT w/ some restrictions) Flip-flop bank on inputs for retiming Hierarchical Interconnect Fixed clock cycle (0.4  m = 4ns) Pipelined Interconnect

22. Hierarchical Interconnect

23. Pipelined Interconnect

24. Input Retiming

25. BLB Cascade Timing

26. HSRA Interconnect

27. Breather 2

28. Mapping How do we get: –from logical design –to programmed array

29. Traditional Design Flow LUT Mapping PlacementRouting Bitstream Generation Tech. Indep. Optimization Config. Data RTL

30. Starting Point RTL –t=A+B –Reg(t,C,clk); Logic –O i =A i  i  C i –C i+1 = A i B i  B i C i  A i C i

31. LUT Map

32. LUT Map Notes Any function of K inputs Flip flops already paid for “Inverters” in logic can always be absorbed into LUTs

33. Placement Maximize locality –minimize number of wires in each channel –minimize length of wires –(but, cannot put everything close) Often start by partitioning/clustering State-of-the-art finish via simulated annealing

34. Place

35. Routing Often done in two passes –Global to determine channel –Detailed to determine actual wires and switches HSRA/Hierarchical –Global implied by hierarchy Difficulty is –limited channels –switchbox connectivity restrictions

36. Route

37. HSRA Design Flow LUT Mapping PartitionPlacement Bitstream Generation Tech. Indep. Optimization Config. Data RTL RoutingRetiming

38. HSRA Netlist View Each LUT has a shift-register bank on input –needs to be deep enough to cover network cycles –tools move registers as needed to cover network registers –currently complain if insufficient –in future will retime design to cover

39. Retime Example

40. Retimed to HSRA

41. Review FPGA Composition –(LUTs, retiming, programmable switching) Commercial FPGA (XC4K) HSRA Mapping –to LUT, place, route, retime …all ready to tackle Exercise SPACE1