1. Xilinx and Nexys2 Tutorial Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University, Houston, TX

2. ELEC 326 Digital Logic Design2 Verilog synthesis+simulation with Xilinx Xilinx Project Navigator Icon on your Desktop

3. ELEC 326 Digital Logic Design3 Open a new project called decoder2to4 Choose a working directory (C:\...\decoder2to4) and name the top level module there (decoder2to4)

4. ELEC 326 Digital Logic Design4 Device options, etc. The next step is to select the target device and its specs from the board (Spartan3E, xc3s500e, fg320); to specify Verilog as the input HDL language

5. ELEC 326 Digital Logic Design5 Create a new top level module decoder2to4 in the project Adding new Verilog source

6. ELEC 326 Digital Logic Design6 Initialize project directory

7. ELEC 326 Digital Logic Design7 Enter the source nUse bottom tabs to select the source file, key in the Verilog description, and save it Design constraints+actions: synthesis+implementation, bit-file generation, etc.

8. 2-to-4 decoder example nUse case statement nNote that output [3:0] y is changed to output reg [3:0] y  No Xilinx option to specify this directly  Hand-code as necessary ELEC 326 Digital Logic Design8

9. User constraint file (UCF) nUCF file for I/O mapping nThe UCF allows us to leverage the switches, LEDs, etc. on the board to interact with the implemented design (see documentation on 326 page too) nAdd new source  Mapping visible on board  Sometime mis-marked  Cross-check with manual ELEC 326 Digital Logic Design9

10. UCF generation ELEC 326 Digital Logic Design10

11. Add I/O constraints nThe mapping assigns switch 1 (available on pin G18) to input W[0], etc. These mappings are visible on the board and also part of the Nexys2 board documentation. ELEC 326 Digital Logic Design11

12. Compile! nSelect the decoder2to4 module and double-click the “Synthesize – XST” button. Note that Xilinx displays all allowed options for the selected file in the project. For example, selecting the io.ucf file does not provide options like synthesis, etc. since it really is not a Verilog module. nSynthesis will take some time.  If successful, you will see a green check-mark nDouble-click “Generate Programming File” to generate the bit-file nYou can expand the synthesis tab and look at the synthesis report, warnings, critical path delay, etc. nErrors and warnings  Heed them and you will learn as you go  Ask labbies ELEC 326 Digital Logic Design12

13. Adding SSD signal nAdd extra output ssd nPulls all seven-segment display limbs up for the decoder, so that you don’t see a faint glow nSame limbs will find use in core of your SS module  UCF entries are handy ELEC 326 Digital Logic Design13

14. UCF for complete design ELEC 326 Digital Logic Design14

15. Generate programming file ELEC 326 Digital Logic Design15

16. Programming the FPGA nOnce the bit-stream is generated, we will configure the FPGA using the boundary-scan port  Boundary-scan and JTAG are features used for post-production test of ICs using very simple shift- register concepts and 4 I/O pins  The parallel-port connector lists these as TDI, TDO, TCLK, and TMS (test data in, …)  Can be used to configure FPGAs using the Adept software (icon below)

17. Programming the FPGA ELEC 326 Digital Logic Design17

18. Programming the FPGA ELEC 326 Digital Logic Design18