1. Software and Hardware Implementation of Cellular Automata for Structural Analysis and Design Zafer Gürdal * & Mark T. Jones ** Virginia Tech *Depts. of Aerospace and Ocean Eng., & Engineering Science and Mechanics **The Bradley Department of Electrical and Computer Engineering 06/17/03 National Institute of Aerospace, Hampton VA Support  NASA LaRC, NRA 98, Innovative Algorithms for Aerospace Engineering Analysis and Optimization, PM: Jarek Sobieski  NASA LaRC, Mechanics and Durability Branch, PM: Damodar Ambur  Virginia Tech, ASPIRES Program

2. CA Software Hardware Implementation June 17, 2003 Outline  Introduction  Evolutionary Design  Elements of Cellular Automata  CA applied to Engineering Design  Truss Domain  Composite Laminate Design  Hardware Implementation  Configurable Computing – FPGAs  CA Implementation Results  Multigrid Acceleration

3. CA Software Hardware Implementation June 17, 2003 Evolutionary Design  Mimic natural evolution of biological systems for structural design  Evolutionary design often relies on local optimality/decision making of independent parts  Examples: Reaction wood Bone growth  Cellular Automata: Decomposition of a seemingly complex macro behavior into basic small local problems

4. CA Software Hardware Implementation June 17, 2003 Evolutionary Design of Structures Evolutionary Design Genetic Algorithms Species ESO,MMD,CA Individual Designs Cellular Automata Local Evolution of Analysis and Design ESO, MMD Local Rules for Design, Global Analysis

5. CA Software Hardware Implementation June 17, 2003 Cellular Automata  Weiner (1946), Ulam (1952), von Neumann (1966) –Automata Networks –Cell Dynamic Scheme  Idealizations of complex natural systems –Flock behavior –Diffusion of gaseous systems –Solidification and crystal growth –Hydrodynamic flow and turbulence  General characteristics –Locality –Vast Parallelism –Simplicity

6. CA Software Hardware Implementation June 17, 2003 Elements of Cellular Automata  Cell Definitions  Lattice Configurations  Neighborhoods  Boundaries  Update rules  Iteration Schemes

7. CA Software Hardware Implementation June 17, 2003 Elements of Cellular Automata  Definition for state of a cell and update rule time step cell ID  Two-dimensional Lattice Configurations Rectangular Triangular Hexagonal Neighborhood cells Center cell

8. CA Software Hardware Implementation June 17, 2003 Neighborhood Definition  Rectangular Neighborhoods von Neumann Moore MvonN N S E W N S E W SE NENW SW N S E W SE NENW SW EE SS WW NN  Boundaries  Periodic  Location Specific

9. CA Software Hardware Implementation June 17, 2003 Update Rule – 2D Truss Domain Analysis Ground Structure uCuC vCvC C N S E NWNW NENE SWSW SE u SE vSE vSE W  Single Cell  Displacement Update:

10. CA Software Hardware Implementation June 17, 2003 Sample Truss Analysis Results UndeformedCA AnalysisFEM Analysis Linear Analysis Nonlinear Analysis Applied force or displacement

11. CA Software Hardware Implementation June 17, 2003 Linear vs. Nonlinear Analysis Linear analysis Nonlinear analysis # of iterations total reaction 1641 iterations 2985 iterations

12. CA Software Hardware Implementation June 17, 2003 Sizing/Design Rules  Local Optimization Formulation  Sequential Move and Size  Fully Stressed Design Geometry & Basic Ground Structure CDF = 1 75 kN 100 kN 40 m 60 m Dense Truss Solution (CDF = 40)

13. CA Software Hardware Implementation June 17, 2003 Design of Fiber Reinforced Panels  Minimum Compliance Design where  (x,y): fiber angle distribution Principal Strain Direction  Minimum Strain Energy Density (Pedersen 1990)

14. CA Software Hardware Implementation June 17, 2003 Panel with a Circular Hole in Shear Optimality Criteria (OC) Design Quarter Panel Model

15. CA Software Hardware Implementation June 17, 2003 Panel with a Circular Hole in Shear Pattern Matching + OC Design Pattern Matching + Discrete Design

16. CA Software Hardware Implementation June 17, 2003 Panel with a Circular Hole in Shear Topology + Orientation Design Topology + Discrete Fiber Orientation

17. CA Software Hardware Implementation June 17, 2003  Domain Modeled === Hardware Domain  Current parallel architectures are limited  Specialized CA machines mimicking CA domains Hardware Integration

18. CA Software Hardware Implementation June 17, 2003 Configurable Computing and Field Programmable Gate Arrays (FPGAs)

19. CA Software Hardware Implementation June 17, 2003 Definitions and Potential  Configurable computers are a relatively new class of computer architecture in which hardware circuits are (re-)configured for a specific algorithm  Offer “ASIC-like” speeds without the cost of designing and fabricating a chip –ASIC cost can run into many millions –General-purpose CPUs are slow  Configurable computers are often built using FPGAs because of their widespread availability (>>$1B market)

20. CA Software Hardware Implementation June 17, 2003 Field Programmable Gate Array (FPGA) Layout  An FPGA consists of a large array of Configurable Logic Blocks (CLBs) - typically 1,000 to 8,000 CLBs per chip  Each CLB contains registers and LUTs, where each LUT can implement a 4-input logic operation  By programming the CLBs and interconnections large circuits can be represented in the FPGA  One Xilinx XC2V4000 FPGA can represent a circuit up to 1M gates

21. CA Software Hardware Implementation June 17, 2003 DINI DN3000k10 Board  DINI DN3000k10 is an FPGA based PCI card  Contains five Xilinx XCV4000 FPGAs connected by a 226 bit wide bus  One of the FPGAs has a separate connection for communicating to a PC via the PCI bus  FPGAs can be configured through the PCI bus or configurations can be stored on board

22. CA Software Hardware Implementation June 17, 2003 Algorithms for FPGAs  Target FPGA strengths: parallel, pipelined, customized –Goal is to have every part of the chip actively computing at the highest possible clock speed  Do: re-think the algorithm to –Expose the natural parallelism –Pipeline time-consuming operations –Examine the precision that is really necessary  Do not: Implement algorithms as you would in software on a traditional computer

23. CA Software Hardware Implementation June 17, 2003 Multiplier Options Usage (% CLBs)* *Percentage of CLBs used in a XC2V4000, the XC2C4000 contains 5760 CLBs

24. CA Software Hardware Implementation June 17, 2003 Application Performance  HokieGene – Genome Matching Project (2003) –Matching engine executes on one FPGA (XC2V1000) –Performs 200 billion cell updates per second –1,200 billion operations per second (1.2 TOPS)  BYU - Network Intrusion Detection Systems (2002) –Hardware implementation uses one FPGA (XC2V1000) –Outperformed software version running on P3 – 750MHz: Up to 400 times more throughput than software version Up to 1000 times less latency than software version  Xilinx – High Performance DES Encryption (2000) –Implemented on one small FPGA (XCV150) –Maximum throughput 10.75 GB/sec –Outperformed best ASIC implementation  University of Texas at Austin – Target Recognition System (2000) –System built using one FPGA (ORCA 40k) and Myrinet interfacing –Capable of processing 900 templates per second –2,800 billion operations per second (2.8 TOPS)

25. CA Software Hardware Implementation June 17, 2003 Iterative Methods for Linear Systems  Consider Jacobi’s method –D x i+1 = (D-A) x i + b –In software, we would select either single or double precision floating point  On a configurable computer we can select any format in which to store/compute value –Choose the desired precision of the solution –Reconstruct the method for fast computation

26. CA Software Hardware Implementation June 17, 2003 Iterative Methods Continued  Re-cast as iterative improvement scheme r i = b - A x i  Compute in n bits  x i = A –1 r i  Compute in k bits x i+1 = x i +  x i = A –1 r i  Compute in n bits  Use Jacobi to solve for  x i in compact, fast k-bit hardware (cost ~ bits 2 )  Thm: Convergence rate is independent of k  Thm: Optimal choice of k ~ n/(# iterations) 1/3

27. CA Software Hardware Implementation June 17, 2003 Convergence  Solution Error vs. Number of Iterations  K= 3,6,9 decimal digits  No difference in convergence rate

28. CA Software Hardware Implementation June 17, 2003 Performance Advantage  Execution Cost (number of bit operations) vs. the size of the matrix  Compares cost of normal vs. modified algorithm  Convergence for each algorithm is identical

29. CA Software Hardware Implementation June 17, 2003 Euler Beam Formulation x y F hh w L,θ L w C,θ C w R,θ R FCFC Control Volume MCMC FRFR MRMR FLFL MLML d(x)  Cell Neighborhood  Cell Equilibrium

30. CA Software Hardware Implementation June 17, 2003 Cellular Automata Model Multiple Cells per Processing Element

31. CA Software Hardware Implementation June 17, 2003 Beam Design  residual  error  correction  Equilibrium Update  Design Update Converged Design Update Converged End Equilibrium Update NO YES

32. CA Software Hardware Implementation June 17, 2003 Algorithm Strategy  The limited precision algorithm illustrated for Jacobi’s method earlier is applied to CA –Much smaller, faster circuits for applying CA rule updates in k-bit operations –Built-in 18x18 multipliers compute residual  Built-in high-speed memories provide –Storage for intermediate and permanent quantities –Many customizable word-lengths –Extremely high memory bandwidth

33. CA Software Hardware Implementation June 17, 2003 Processing Element

34. CA Software Hardware Implementation June 17, 2003 FPGA Performance Cell Updates Per Second (Millions)

35. CA Software Hardware Implementation June 17, 2003 CA Performance

36. CA Software Hardware Implementation June 17, 2003 Multigrid Acceleration x y F lattice 8h lattice 4h lattice 2h lattice h E : Equilibrium update to convergence : Equilibrium updated α times S S S S E S S S h 2h2h 4h4h 8h8h lattice V - cycle S S S E S E S S S E S E S S S h 2h2h 4h4h 8h8h lattice W - cycle : Restriction (on r) : Prolongation (on e)

37. CA Software Hardware Implementation June 17, 2003 Prolongation lattice 2h lattice h

38. CA Software Hardware Implementation June 17, 2003 Prolongation/Restriction lattice 2h lattice h  Correction Prolongation  Residual Restriction where Prolongation Operator

39. CA Software Hardware Implementation June 17, 2003 Design with 5 Cells: Design with 17 Cells: Design with 65 Cells: ~ Design with 257 Cells: ~ ~ Design with 3 Cells: Nested Iteration for MG accelerated CA d(x)

40. CA Software Hardware Implementation June 17, 2003 CA Design Performance with Full MG 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 1101001000 Number of Cells Total number of cell updates

41. CA Software Hardware Implementation June 17, 2003 Concluding Remarks  Summary –CA paradigm has been demonstrated for various structural systems –CA paradigm matches well with Configurable Computing acceleration –Full Multigrid acceleration for CA improves design convergence  Future Work –Expand the design capabilities in terms of structural details and the types of field problems that can be solved –Tools that will enable engineers to effortlessly use configurable computers for CA applications –Continue to investigate algorithms to improve CA performance