Presentation is loading. Please wait.

Presentation is loading. Please wait.

K&H MFG. Co., LTD. Manufacturer, Exporter & Importer for Educational Equipment & Measuring Instrument CIC-310 CPLD/FPGA Development System.

Published byAnis Potter Modified over 8 years ago

Similar presentations

Presentation on theme: "K&H MFG. Co., LTD. Manufacturer, Exporter & Importer for Educational Equipment & Measuring Instrument CIC-310 CPLD/FPGA Development System."— Presentation transcript:

1 K&H MFG. Co., LTD. Manufacturer, Exporter & Importer for Educational Equipment & Measuring Instrument CIC-310 CPLD/FPGA Development System

2 CIC-310 CPLD/FPGA Development System § Hardware Overview --- System Overview --- Development Board --- Experiment Board § Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager § Experiments --- List of experiments --- Implementations § CPLD / FPGA Background

3 CIC-310 CPLD/FPGA Development System § Hardware Overview --- System Overview --- Development Board --- Experiment Board § Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager § Experiments --- List of experiments --- Implementations § CPLD / FPGA Background

4 Traditional design flow of the logic circuit In = A, B, C, D... Out = X, Y … Design specification Truth table Manual X = (Ā+B+C) (B+D) ( Ā+D ) Boolean expression Manual (K-map) § CPLD/FPGA BACKGROUND – (1) Implement on several ICs Manual

5 PAL – Programmable Array Logic Programmable AND array followed by fixed fan-in OR gates ABC AND plane Programmable switch or fuse

6 PLD - Programmable Logic Device ABC AND plane PLD DQ Q S0 S1 B D C A Q HDL : Hardware Description Language

7 CPLD (Complex PLD) Structure Integration of several PLD blocks with a programmable interconnect on a single chip PLD Block PLD Block PLD Block PLD Block Interconnection Matrix I/O Block PLD Block PLD Block PLD Block PLD Block I/O Block Interconnection Matrix

8 FPGA Look-Up Tables (LUT) Look-up table with N-inputs can be used to implement any combinatorial function of N inputs LUT is programmed with the truth-table LUT A B C D Z A B C D Z Truth-tableGate implementation LUT implementation

9 FPGAs vs. CPLDs Are FPGAs and CPLDs the same thing? No. Both are programmable digital logic chips. Both are made by the same companies. But they have different characteristics. FPGAs are "fine-grain" devices. That means that they contain a lot (up to 100000) of tiny blocks of logic with flip-flops. CPLDs are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with flip-flops. FPGAs are RAM based. They need to be "downloaded" (configured) at each power-up. CPLDs are EEPROM based. They are active at power-up (i.e. as long as they've been programmed at least once...). CPLDs have a faster input-to-output timings than FPGAs (because of their coarse-grain architecture, one block of logic can hold a big equation), so are better suited for microprocessor decoding logic for example than FPGAs. FPGAs have special routing resources to implement efficiently binary counters and arithmetic functions (adders, comparators...). CPLDs do not. FPGAs can contain very large digital designs, while CPLDs can contain small designs only.

10 FPGA & CPLD FPGAs are RAM based. They need to be "downloaded" (configured) at each power-up. CPLDs are EEPROM based. They are active at power-up (i.e. as long as they've been programmed at least once...). FPGAs can contain very large digital designs, while CPLDs can contain small designs only. CPLDs have a faster input-to-output timings

11 Modern design flow of the logic circuit Design specification In = A, B, C, D... Out = X, Y … Implement on ONE CPLD/FPGA chip Automatic Design description HDL Syntax Manual (programming) Save lots of time!!! § CPLD/FPGA BACKGROUND – (2)

12 FPGA/CPLD Counter Converter Timer PWM MPU GPIO Control GPIO Control Decoder MCU Memory ALU SOPC (System On Programmable Chip)

13

14 CIC-310 CPLD/FPGA Development System § Hardware Overview --- System Overview --- Development Board --- Experiment Board § Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager § Experiments --- List of experiments --- Implementations § CPLD / FPGA Background

15 § System Overview CIC-310 provides digital system designers with an economical solution for hardware verification or students with an efficient learning of digital system design. CPLD/FPGA Development Board Experiment Board + CIC-310 =

16 Altera 8k/10k RAM-based FPGA RS232 connector Max. 32kB SEEPROM 7.5C DC Power 89C2051 for load the configuration data to FPGA or SEEPROM devices with data compression techniques HIN230 for RS-232 transmitters/receivers interface circuits Reset button: Reset connection to PC Program selector jumper 11.0592MHz Xosc § Hardware Overview – Development Board

17 Logic Switch Input Section Input Status Logic LED Display Output Logic LED Display 20MHz X’TRAL OSC 6-Digit Parallel-Serial 7-segment Display RC Oscillator Pulse generator SW and Keypad Section 5 x 7 DOT LED display 16-Segment Display Section § Hardware Overview – Experiment Board

18 CIC-310 CPLD/FPGA Development System § Hardware Overview --- System Overview --- Development Board --- Experiment Board § Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager § Experiments --- List of experiments --- Implementations § CPLD / FPGA Background

19 § EXPERIMENT FLOWCHART Personal Computer Development Board Rs-232 Programming Download the program Windows 98/2000/XP Experiment Board Show the result Program manager

20 § Programming Flowchart

21 Download the program to FPGA and execute the program Add the program to SEEPROM Execute the program from SEEPROM § Program manager functions

22 CIC-310 CPLD/FPGA Development System § Hardware Overview --- System Overview --- Development Board --- Experiment Board § Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager § Experiments --- List of experiments --- Implementations § CPLD / FPGA Background

23 § LIST OF EXPERIMENTS Combinational logic circuits –Applications of ALUs –Encoder / Decoder –Alpha-Nemaric LED display –Multiplexer / Demultiplexer Sequential logic circuits –Flip-flop circuits –Applications of counters –Frequency synthesizers / Shift Registers Dynamic 5x7 LED matrix display 4x4 keypad of matrixes More than 50 examples in the experimental manual!!!

24 Implementations Exp1 : Step by step design of basic logic circuit by Graphic and Text Editor Exp2 : Binary-to-16-segment decoder Exp3: Counters Exp4: 5X7 DOT matrix display Exp5: Keypad

25 Input: P01, P02, P03, P04, P06, P07, P08 Output : P55, P56, P57, P58 Exp1: Basic logic circuit design (Primal.gdf) Specification: Input: DIP switches Output: LED display Relation: P55 = !P01 P56 = P02 & P03 P57 = P04 # P06 P58 = P07 $ P08 ! => NOT & => AND # => OR $ => XOR

26 P01 P02 P03 P04 P06 P07 P08 P55 P56 P57 P58 Step 1: Programming by graphic editor

27 Step 3: Save&Compile (Max+Plus II / Compiler) Step 2: Assign Devices (Assign / Devices)

28 Step 4: Simulation ( 1. Max+Plus II / Waveform Editor ) ( 2. Max+Plus II / Simulator)

29 Step 4: Pin Assignment ( Max+Plus II / Floorplan Editor)

30 Step 5: Download the program Download the program to FPGA and execute the program Add the program to SEEPROM Execute the program from SEEPROM

31 Program by Text Editor --- Primal.tdf The rest design steps are the same

32 Exp2: Binary-to-16-segment decoder Specification: Input: DIP switches Output: 16-segment display Relation: 6 bit inputs are decoded to 16-segment display as: Numerical number : 0~9 Alphabet letters : A~Z Math Operators: ＊, +,-,/ Why you need 6-bit input? Input: P01, P02, P03, P04, P06, P07 Output : 16-segment display 0~9  10 A~Z  26 ＊,+,-,/  4 10+26+4=40 2^6 = 64 > 40

33 Program by Text Editor --- 16segb.tdf... a1a2b1b2c1c2d1d2e1e2g1g2h1h2i1i2/p 1234567891011121314151617 Symbol Position

34 16- segment FPGA 8K 10k 16- segment FPGA 8K 10k A1P13 P16E2P23 P27 A2P14 P17G1P24 P28 B1P15 P18G2P25 P29 B2P16 P19H1P27 P30 C1P18 P21H2P28 P35 C2P19 P22I1P29 P36 D1P20 P23I2P30 P37 D2P21 P24DPP63 P64 E1P22 P25C-SELP23 P27 Table 1-6 16 segment display pin-out (8k-84pin) 1 2 Pin Assignment (1)

35 P13P14 P15 P16 P18P19 P20 P21 P22 P23 P24 P25 P27 P28 P29 P30 P63 a1a2b1b2c1c2d1d2e1e2g1g2h1h2i1i2/p 012345678910111213141516 1314151618192021222324252728293063 Symbol Segment Pin Pin Assignment (2)

36 Show Result 1617181921222324252728 3035363764 a1a2b1b2c1c2d1d2e1e2g1g2h1h2i1i2/p Symbol FPGA Pin FPGA JP8JP9JP10 JP8 JP9 JP10

37 Exp3: Counters Specification: Input: Enable: Sw1_1 Reset: Sw1_2 Clock: SWP3 Output: LED display Relation: The 4-bit ripple counter repeats itself for every 2^4 (16) clock pulses. : Input: Sw1_1, p01 (Enable) Sw1_2, P02 (Reset) SWP3, P83 (Clock) Output : P55, P56, P57, P58 Construct a 4-bit asynchronous counter by T flip-flops

38 Asynchronous Counter: Program by Graphic Editor --- 4slcnt.gdf

39 Asynchronous Counter: Program by Text Editor --- 4slcnt.gdf TFF primitive

40 Asynchronous Counter: Program by Text Editor --- 4slcnt.gdf FF[]=FF[]-1;

41 Synchronous Counter: Program by Graphic Editor --- ptcnt8.gdf

42 Synchronous Counter: Program by Text Editor --- ptcnt8t.tdf

43 Asynchronous Counter Synchronous Counter Delay Matrix

44 4 Digit Counter: Frequency Counter --- pdec9999.tdf Input: Clock Output: LED Display (Counting 0~9999 in binary format)

45 SASBSCSDSESFSG 7 segment displayer --- 7segd.tdf Input: DIP switch Output: 7 segment displayer

46 4 Digit Counter: Parallel mode --- 4dec7sp.tdf Require Pins: 6 x 4 = 24 01234576890123457689 0123457689

47 4 Digit Counter: Serial Scan mode --- 4dec7sn.tdf Require Pins: 6 x 1 + 4 = 10 01234500 0 0

48 PA1 PA2 PA3 PA7 PA6 PA4 PA5 P13 P14 P15 P20 P19 P16 P18 P22P23P24P25P27 5x7 Matrix DOT display (dot_test.tdf) Exp4: 5x7 dot matrix display

49 5x7 DOT Matrix display (dot_test.tdf) PA1 PA2 PA3 PA7 PA6 PA4 PA5 P13 P14 P15 P20 P19 P16 P18 P22P23P24P25P27 TRY 57dots.hex !!! 1 0 1 0 1 0 1 Counter

50 Individual Mode --- require 16 ports Scan Mode --- require 8 ports P34 P35 P36 P37 P39 P40 P41 P42 P43 P44 P45 P46 P48 P49 P50 P51 Parallel Mode => PKI1, PKI2, PKI3 Serial Mode => SCN1, SCN2, SCN3 Exp5: Keypad

51 A: Mechanical Shock Wave Test ( key_test.tdf ) Input: SW0 Output : P53, P54, P58, P59

52 B: Debounce Circuit Design (debounce_test.tdf ) Detect 16 times

53 C: Keypad Circuit Design with debounce function --- Parallel Mode (16_KEY_Parallel.tdf) Parallel Mode => PKI1, PKI2, PKI3 Serial Mode => SCN1, SCN2, SCN3

54 D: Keypad Circuit Design with debounce function --- Scan Mode (16_key_scan.tdf) Parallel Mode => PKI1, PKI2, PKI3 Serial Mode => SCN1, SCN2, SCN3

55 DEB 1  SR[ ]=SR[ ] 0  SR[ ]=SR[ ]+1 S[1..0] DECODE 00 01 10 11 DEB [3..0]

56 E: Keypad Circuit Design with debounce function & 7-segment display (.tdf)

57 CPLD FPGA DSP MPU

Download ppt "K&H MFG. Co., LTD. Manufacturer, Exporter & Importer for Educational Equipment & Measuring Instrument CIC-310 CPLD/FPGA Development System."

Similar presentations

FPGA (Field Programmable Gate Array)

FPGA (Field Programmable Gate Array)
Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.

Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Configurations Read Only Memory (ROM) – –a fixed array of AND gates.

1 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Configurations Read Only Memory (ROM) – –a fixed array of AND gates.
Programmable Interval Timer

Programmable Interval Timer
Survey of Reconfigurable Logic Technologies

Survey of Reconfigurable Logic Technologies
EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.

EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.
Programmable Logic Devices

Programmable Logic Devices
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.
Implementing Logic Gates and Circuits Discussion D5.1.

Implementing Logic Gates and Circuits Discussion D5.1.
CHAPTER 1 Digital Concepts

CHAPTER 1 Digital Concepts
Counter Circuits and VHDL State Machines

Counter Circuits and VHDL State Machines
Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.

Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.
ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.

ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.
02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
Programmable logic and FPGA

Programmable logic and FPGA
1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
Multiplexers, Decoders, and Programmable Logic Devices

Multiplexers, Decoders, and Programmable Logic Devices
February 4, 2002 John Wawrzynek

February 4, 2002 John Wawrzynek
Fundamentals of Digital Logic B. Furman 25NOV2014.

Fundamentals of Digital Logic B. Furman 25NOV2014.
ECE 331 – Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #16) The slides included herein were taken.

ECE 331 – Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #16) The slides included herein were taken.

Similar presentations

Ads by Google