1. 混合式 CMOS/PTL 合成器嵌入在 標準元件庫之 IC 設計流程 Presenter: Ming-Yu Tsai

2. Ming-Yu Tsai 1 Outline Introduction Introduction Overview Cell Based Design Flow Overview Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Application Application Conclusion Conclusion

3. Ming-Yu Tsai 2 Outline Introduction Introduction –PTL cells –PTL synthesis Overview Cell Based Design Flow Overview Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Application Application Conclusion Conclusion

4. Ming-Yu Tsai 3 Introduction What’s PTL What’s PTL –Pass-Transistor-Logic (PTL)

5. Ming-Yu Tsai 4 Threshold Drops V DD V DD  0 0  V DD CLCL CLCL V DD 0  V DD - V Tn CLCL V DD V DD  |V Tp | CLCL S DS D V GS S SD D V GS >|V t |

6. Ming-Yu Tsai 5 MOS Transistors in Series/Parallel

7. Ming-Yu Tsai 6 Pass Transistor Logic (PTL) N transistors instead of 2N N transistors instead of 2N No static power consumption No static power consumption Bidirectional (versus undirectional) Bidirectional (versus undirectional) A B F B 0 A 0 B B = A  B F

8. Ming-Yu Tsai 7 Advantages of PTL PTL cells PTL cells –Small area –Better performance for MUX- and XOR-based circuits –Less power consumption PTL synthesizer PTL synthesizer –Only two types of cells – 2-to-1 multiplexers (MUX) – Inverters –Regular CMOS inverter –Special inverter with a feedback weak pMOS –When process technology is updated – Easy to update all of PTL cell circuits

9. Ming-Yu Tsai 8 Different Categories of PTL Circuit Designs (1/2)

10. Ming-Yu Tsai 9 Different Categories of PTL Circuit Designs (2/2) Dual-rail Dual-rail –CPL (Complementary Pass-transistor Logic) –DPL (Double Pass-transistor Logic) –SRPL(Swing-Restore Pass-transistor Logic) –EEPL (Energy Economized Pass transistor Logic) –PPL (Push-Pull Pass transistor Logic) –CVSL (Cascode Voltage Switch Logic) –DCVSPG (Differential Cascode Voltage Switch with Pass-Gate) Single-rail Single-rail –LEAP (LEAn-integration Pass-transistor logic) –CMOSTG (CMOS with Transmission Gate) –PTL_n & PTL_np

11. Ming-Yu Tsai 10 PTL cells (Dual-rail) CPL SRPL DPL

12. Ming-Yu Tsai 11 PTL Cells (Single-rail) LEAP CMOSTG PTL_n PTL_np

13. Ming-Yu Tsai 12 Tradition of PTL Synthesis (1/2) BDD BDD –Binary Decision Diagram – MUX-based Example Example

14. Ming-Yu Tsai 13 Why Need Using BDDs Because employing BDDs for PTL ensures a sneak-path-free implementation Because employing BDDs for PTL ensures a sneak-path-free implementation –Sneak-path – Both two nMOS switches are turned on at the same time –resulting in larger power dissipation

15. Ming-Yu Tsai 14 Tradition of PTL Synthesis (2/2) Single-level Single-level –Small area –long critical path – depend on # of primary inputs Multi-level Multi-level –Large area –Short critical path Single-level Multi-level

16. Ming-Yu Tsai 15 Outline Introduction Introduction Overview Cell Based Design Flow Overview Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Application Application Conclusion Conclusion

17. Ming-Yu Tsai 16 Design Abstraction Levels (1/2) SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G Cell based design

18. Ming-Yu Tsai 17 Design Abstraction Levels (2/2) System interface 介面電路介面電路 System A/DRegister RAM Block or Algorithm Schematic representation Physical layout Y VDD VSS Devices and connections

19. Ming-Yu Tsai 18 Cell-Based Design Flow

20. Ming-Yu Tsai 19 Logic Synthesis Synthesis = Translation + Optimization + Mapping Synthesis = Translation + Optimization + Mapping Translation =HDL code → Generic Boolean (GTECH) Translation =HDL code → Generic Boolean (GTECH) –It’s technology independence Optimize + Map = Generic Boolean → Target Technology Optimize + Map = Generic Boolean → Target Technology –It’s technology dependence

21. Ming-Yu Tsai 20 Layout view of C432

22. Ming-Yu Tsai 21 IC Fabrication

23. Ming-Yu Tsai 22 Cell-Based Design Flow V.S. Software Design Flow

24. Ming-Yu Tsai 23 Outline Introduction Introduction Overview Cell Based Design Flow Overview Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow –Basic PTL cells –Pure PTL synthesis method Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Application Application Conclusion Conclusion

25. Ming-Yu Tsai 24 Basic PTL Cells 2-to-1 multiplexer 2-to-1 multiplexer –MUX Regular CMOS inverter Regular CMOS inverter –INV Special inverter with a feedback weak pMOS Special inverter with a feedback weak pMOS –PINV – Level-restoring PINV Design

26. Ming-Yu Tsai 25 Why Need Insert PINV (1/2) In = 0  V DD V DD x Out 0.5/0.25 1.5/0.25 Time, ns Voltage, V In Out x = 1.8V D S B

27. Ming-Yu Tsai 26 Why Need Insert PINV (2/2)

28. Ming-Yu Tsai 27 Circuit Design of PINV (1/2) MOS size ratio of PINV MOS size ratio of PINV –Logic “0” passing through nMOS is strong –Logic “1” passing through nMOS is weak Need low-skew inverter design Need low-skew inverter design –UMC 90n – 1/2.5

29. Ming-Yu Tsai 28 Circuit Design of PINV (2/2) Feedback pMOS Feedback pMOS –A ratioed circuit design causing temporary fighting –Avoid malfunction – Keep the feedback pMOS as small as possible – Set a restriction on the maximum fanout load

30. Ming-Yu Tsai 29 Pure PTL Synthesis Embedded in Standard Cell-Based Design Flow

31. Ming-Yu Tsai 30 PTL Library Logic Cells One-level PTL logic cell circuit One-level PTL logic cell circuit Two-level PTL logic cell circuits Two-level PTL logic cell circuits

32. Ming-Yu Tsai 31 One-Level PTL Logic Cells

33. Ming-Yu Tsai 32 Selection of One-level PTL Logic Cells Using all the one-level PTL logic cells is best Using all the one-level PTL logic cells is best

34. Ming-Yu Tsai 33 Multi-Level PTL Logic Cells Case I: no clear advantage Case I: no clear advantage Case II: much better circuit Case II: much better circuit

35. Ming-Yu Tsai 34 PTL Logic Simplification Remove redundant inverters Remove redundant inverters –called buffer elimination Use simple regular inverters Use simple regular inverters –for example, in primary inputs

36. Ming-Yu Tsai 35 Buffer Elimination (1/3) Method Method –If possible, move PINV from output of MUX to the two inputs Four exceptions Four exceptions –The PINV cannot be moved – k-level rule (k=3 )

37. Ming-Yu Tsai 36 Buffer Elimination (2/3) Inverter Elimination (three cases) Inverter Elimination (three cases)

38. Ming-Yu Tsai 37 Example (C17)

39. Ming-Yu Tsai 38 Buffer Elimination (3/3) Number of inverters before and after buffer elimination Number of inverters before and after buffer elimination –54%~60% saving rate

40. Ming-Yu Tsai 39 Experimental Results UMC 90nm technology UMC 90nm technology Area of some PTL circuits are larger than CMOS Area of some PTL circuits are larger than CMOS –layout problem of pure nMOS cells

41. Ming-Yu Tsai 40 Layout Problems of PTL Basic Cells Generic λ design rules Generic λ design rules –need safe distance along the cell boundary Solutions Solutions –Separation of rows –No pure nMOS cells

42. Ming-Yu Tsai 41 Why Need Design Rule (1/2)

43. Ming-Yu Tsai 42 Why Need Design Rule (2/2)

44. Ming-Yu Tsai 43 Layout Compaction Methods Separation of rows for MUX and PINV cells Separation of rows for MUX and PINV cells

45. Ming-Yu Tsai 44 Experimental Results Separation of rows Separation of rows ISCAS’85 benchmark circuit C432 ISCAS’85 benchmark circuit C432

46. Ming-Yu Tsai 45 Merging basic PTL cells (1/2) Eliminate pure nMOS cells Eliminate pure nMOS cells –Merge of Different Types of Basic Cells

47. Ming-Yu Tsai 46 Merging basic PTL cells (2/2) –Merge of Same Types of Basic Cells

48. Ming-Yu Tsai 47 Experimental Results Merge of basic PTL cells Merge of basic PTL cells ISCAS’85 benchmark circuit C432 ISCAS’85 benchmark circuit C432

49. Ming-Yu Tsai 48 Synthesis Results Use merging of basic PTL cells Use merging of basic PTL cells Compare with CMOS cell library Compare with CMOS cell library –area-optimization constraint –better area, power and area-delay-power product

50. Ming-Yu Tsai 49 Outline Introduction Introduction Overview Cell Based Design Flow Overview Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Application Application Conclusion Conclusion

51. Ming-Yu Tsai 50 Observations from Pure PTL Synthesis CMOS is in general faster than PTL CMOS is in general faster than PTL –Critical path uses CMOS cells –Non-critical path uses PTL cells – To reduce area and power Problems with timing estimation Problems with timing estimation –Some optimizations after PTL synthesis – Buffer Elimination – Layout compaction –Problems – Final circuits might not satisfy the original design constraints – Cause timing violation problems

52. Ming-Yu Tsai 51 PTL V.S. CMOS (1/2) [source] R.-S. Shelar and S.-S. Sapatnekar, “BDD Decomposition for Delay Oriented Pass Transistor Logic Synthesis”, IEEE Trans. VLSI Systems, Vol. 13, No. 8, pp. 957-970, Aug. 2005.

53. Ming-Yu Tsai 52 PTL V.S. CMOS (2/2)

54. Ming-Yu Tsai 53 Hybrid PTL/CMOS Synthesis Flow PTL basic physical cells PTL basic physical cells –MUX – include an inverter –INV –PINV

55. Ming-Yu Tsai 54 One-Level PTL Logic Cells

56. Ming-Yu Tsai 55 Multi-Level PTL Logic Cells n-level PTL logic functions n-level PTL logic functions – Each input signal – {V DD, GND, variable} –Without any simplification – PTL logic cells Three-level PTL logic cells Three-level PTL logic cells –4014 cells (after simplication) –Examples

57. Ming-Yu Tsai 56 PTL Logic Cells for XOR 2-input XOR 2-input XOR 3-input XOR 3-input XOR –Method 1 –Method 2

58. Ming-Yu Tsai 57 Cell Characterization for PTL Logic Cells (1/3) Example Example –CMOS AND3 + level-3 PTL cell – delay calculation for separate cells – more accurate delay – difference of the above two delay calculations

59. Ming-Yu Tsai 58 Cell Characterization for PTL Logic Cells (2/3)

60. Ming-Yu Tsai 59 Cell Characterization for PTL Logic Cells (3/3) Solution Solution –model drain input capacitance (at node 3) of the three-level PTL logic cell as instead of Comparison with SPICE simulation Comparison with SPICE simulation

61. Ming-Yu Tsai 60 Some Improvements for PTL Logic Cells MUX_NP MUX_NP – When one drain input of MUX is always connected to V DD Inverter reduction Inverter reduction

62. Ming-Yu Tsai 61 Experimental Results (1/2) Synthesis results using UMC 90nm technology Synthesis results using UMC 90nm technology –Post-layout simulation

63. Ming-Yu Tsai 62 Experimental Results (2/2) Cell utilization rate (%) for hybrid PTL/CMOS synthesis Critical paths with delay-optimized synthesis constraint

64. Ming-Yu Tsai 63 Outline Introduction Introduction Overview Cell Based Design Flow Overview Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Application Application –Reciprocal Function with Hybrid Piecewise polynomial and Newton-Raphson Method Conclusion Conclusion

65. Ming-Yu Tsai 64 Piecewise Polynomial Method (1/3) polynomial Approximation polynomial Approximation Degree-n means that the approach have x n

66. Ming-Yu Tsai 65 Piecewise Polynomial Method (2/3) f(x)=log 2 x,n=5,m=2

67. Ming-Yu Tsai 66 Piecewise Polynomial Method (3/3) Architecture for degree-n Architecture for degree-n 66

68. Ming-Yu Tsai 67 Newton-Raphson (NR) method

69. Ming-Yu Tsai 68 Error Analysis of NR for reciprocal (1/2) The Error is The Error is So x i is So x i is Inserting x i into the will yield Inserting x i into the will yield

70. Ming-Yu Tsai 69 Error Analysis of NR for reciprocal (2/2) Similar Similar Proportional to the square of one previous error Proportional to the square of one previous error

71. Ming-Yu Tsai 70 Reciprocal Function Unit Using Hybrid Piecewise Polynomial and Newton-Raphson polynomial of degree 2 polynomial of degree 2 Newton Raphson (NR) iterations Newton Raphson (NR) iterations

72. Ming-Yu Tsai 71 Unified Architecture Approximation of 1/d with accuracy of fractional bits Approximation of 1/d with accuracy of fractional bits –According to our experiments – required full precision required full precision –

73. Ming-Yu Tsai 72 Sub-Word-Sharing Architecture Multiplier in Newton Raphson operation Multiplier in Newton Raphson operation – Multiplier in Piecewise operation Multiplier in Piecewise operation – – Multi-operand Adder Multi-operand Adder –3-operand – instead of 5-operand waste merge

74. Ming-Yu Tsai 73 Sub-Word-Sharing Architecture (Mult-2) (1/3) Operand assignment for the multiplier

75. Ming-Yu Tsai 74 Sub-Word-Sharing Architecture (Mult-2) (2/3)

76. Ming-Yu Tsai 75 Sub-Word-Sharing Architecture (Mult-2) (3/3)

77. Ming-Yu Tsai 76 Comparison of Major Components in Different Architectures [P1] M. J. Schulte, I. E. Stine, and K.E. Wires, “High-speed reciprocal approximations,” Proc. 31st Asilomar Conf. On Signals, Circuits and Systems, pp:1178-1182, 1998. [P2] K. Umut and A. Ahmet, “Design and Implementation of Reciprocal Unit Using Table Look-up and Newton-Raphson Iteration,” Proc. Euromicro Systems on Digital System Design, pp. 249-253, 2004. [P3] J. A. Pineiro and J.D. Bruguera, “High-speed double-precision computation of reciprocal, division, square root, and inverse square root,” IEEE Trans. on Computers, Vol. 51, No. 12, pp. 1377-1388, Dec.. 2002. [P2][P1][P3]

78. Ming-Yu Tsai 77 Estimation Delay and Area Model

79. Ming-Yu Tsai 78 ROM (1/2)

80. Ming-Yu Tsai 79 ROM (2/2) For UMC 90n technology For UMC 90n technology

81. Ming-Yu Tsai 80 Synthesis Results (1/2) Area comparison Area comparison –AO and DO – Save 38%~46% Delay comparison Delay comparison –AO – Save as 20% –DO – Save as 1%

82. Ming-Yu Tsai 81 Synthesis Results (2/2) XOR-based cells XOR-based cells –used in Wallace tree – 3-2 counter MUX-based cells MUX-based cells –used in selection unit – 22%~27%

83. Ming-Yu Tsai 82 Outline Introduction Introduction Overview Cell Based Design Flow Overview Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Pure PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Hybrid CMOS/PTL Synthesis Embedded in Cell Based Design Flow Application Application Conclusion Conclusion

84. Ming-Yu Tsai 83 Conclusion Novel hybrid PTL/CMOS synthesis methodology Novel hybrid PTL/CMOS synthesis methodology –Can be easily embedded in the standard cell- based design flow Hybrid CMOS/PTL leads to best results Hybrid CMOS/PTL leads to best results –area-optimized or delay-optimized synthesis

85. Ming-Yu Tsai 84 Must-Have Attitude Your Health Is Indispensable Your Health Is Indispensable Time Is Most Important Constraint Time Is Most Important Constraint Help Your Boss Help Your Boss Promise Your Promise Promise Your Promise Don't Overestimate Others, Underestimate Yourself Don't Overestimate Others, Underestimate Yourself Work Smart & Work Right

86. Ming-Yu Tsai 85 Thanks for your attention!