1. CMOS Design Methodologies

2. The Design Problem Source: sematech97
A growing gap between design complexity and design productivity

3. Design Methodology
Design process traverses iteratively between three abstractions: behavior, structure, and geometry
More and more automation for each of these steps

4. Design Analysis and Verification
Accounts for largest fraction of design time
More efficient when done at higher levels of abstraction - selection of correct analysis level can save multiple orders of magnitude in verification time
Two major approaches:
Simulation
Verification

5. Digital Data treated as Analog Signal
Circuit Simulation
Both Time and Data treated as Analog Quantities
Also complicated by presence of non-linear elements
(relaxed in timing simulation)

6. Circuit versus Switch-Level Simulation

7. Design analysis and simulation
Spice - exact but time consuming
discrete time steps
circuit models
timing simulation with partitioning and relaxation method

8. Gate level simulation faster than switch level functional simulation
VHDL description used

9. Structural Description of Accumulator
Design defined as composition of
register and full-adder cells (“netlist”)
Data represented as {0,1,Z}
Time discretized and progresses with
unit steps
Description language: VHDL
Other options: schematics, Verilog

10. Behavioral Description of Accumulator
Design described as set of input-output
relations, regardless of chosen
implementation
Data described at higher abstraction
level (“integer”)

11. Behavioral simulation of accumulator
Discrete time
Integer data
(Synopsys Waves display tool)

12. Design verification Electrical verification
checking number of inversions between two C2MOS gates
checking pull-up and pull down ratio in pseudo-NMOS gates
checking minimum driver size to maintain rise and fall times
checking charge sharing to satisfy noise-margins

13. Design verification Timing verification Spice too long simulation time
RC delay estimated using Penfield-Rubinstein-Horowitz method
identification of critical path (avoid false paths)

14. Timing Verification Enumerates and rank orders critical timing paths
Critical path
Enumerates and rank
orders critical timing paths
No simulation needed!
(Synopsys-Epic Pathmill)

15. Design verification Formal verification
components described behaviorally
circuit model obtained from component models
resulting circuit behavior computed with design specifications
no generally acceptable verifier exists

16. Implementation approaches

17. Custom circuit design labor intensive high time-to-market
cost amortized over a large volume
reuse as a library cell
was popular in early designs
layout editor, DRC, circuit extraction

18. Layout editor 1. Polygon based (Magic) 2. Symbolic layout
transistor symbols
relative positioning
compaction
stick diagram description
design rules automatically satisfied
automatic pitch matching

19. Custom Design – Layout Editor
Magic Layout Editor
(UC Berkeley)

20. Symbolic Layout Dimensionless layout entities
Only topology is important
Final layout generated by “compaction” program
Stick diagram of inverter

21. Design rule checking
on-line DRC rules checked and errors flagged during layout
batch DRC post design verification

22. Circuit extraction Circuit schematic derived from layout
transistors are build with proper geometry
parasitic capacitances and resistances evaluated
extraction of inductance requires 3D analysis

24. Cell-based design reduced cost reduced time
reduced integration density
reduced performance

25. Cell-based design standard cell compiled cells module generators
macrocell place and route

26. Standard cell
library contains basic logic cells - inverter, AND/NAND, OR/NOR, XOR/NXOR, flip-flop - AOI, MUX, adder, compactor, counter, decoder, encoder,
fan-in and fan-out specified
schematic uses cells from library
layout automatically generated

27. Standard cell cells have equal heights
cell rows separated by routing channels

28. Standard cell design

29. Standard cell layout and description

30. Standard cell
large design cost amortized over a large number of designs
large number of different cells with different fan-ins
large fan-out for cells to be used in different designs
synthesis tools made standard cell design popular
standard cell design outperform PLA in area and speed
standard cell benefit from multi level logic synthesis

31. Compiled cell cell layout generated on the fly
transistor or gate level netlist used with transistor size specified
layout densities approach that of human designers
Circuit schematics
with
transistor sizing

32. Compiled cell
Generated layout

33. Automatic pitch matching

34. Module generators
logic level cells not efficient for subcircuit design - shifters, adders, multipliers, data paths, PLAs, counters, memories
Macrocell generators use design parameters like number of bits
data path compilers use bit slice modules and repeat them N times generate interconnections between modules

35. Datapath compilers
Feedtroughs used to improve routing

36. Datapath compiler
results
Datapath compilers

37. Macrocell place and route
channel routing metal 2 horizontal segments - metal 1 vertical segments
over the block routing (3-6 metal layers used)

38. Macrocell place and route

40. Array-based design implementation
To avoid slow fabrication process which
takes 3-4 weeks :
mask programmable arrays
fuse based FPGAs
nonvolatile FPGAs
RAM based FPGAs

41. Mask programmable arrays
gate-array similar to standard cell
sea-of-gate routed over the cells (high density) - wires added to make logic gates
challenge in design is to utilize the maximum cell capacity
utilization < 75% for random logic design

42. Mask programmable arrays

43. Macrocell Design Methodology
Floorplan:
Defines overall
topology of design,
relative placement of
modules, and global
routes of busses,
supplies, and clocks
Interconnect Bus
Routing Channel

44. Macrocell-Based Design Example
SRAM
SRAM
Data paths
Routing Channel
Standard cells
Video-encoder chip
[Brodersen92]

45. Gate Array — Sea-of-gates
Uncommited
Cell
Committed
Cell (4-input NOR)

46. Sea-of-gate Primitive Cells
Using oxide-isolation
Using gate-isolation

47. Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K
(0.6 mm CMOS)

48. Prewired Arrays
Categories of prewired arrays (or field-programmable devices):
Fuse-based (program-once)
Non-volatile EPROM based
RAM based

49. Programmable Logic Devices
PAL
PLA
PROM

50. Fuse-based FPGA’s
Actel
sea-of-gate
and standard
cell approach

51. Fuse-based FPGA’s Example : XOR gate obtained by setting :
A=1, B=0, C=0, D=1,
SA=SB=In1,
S0=S1=In2

52. Fuse-based FPGA’s
Anti-fuse provides short (low resistance) when blown out

53. Nonvolatile FPGA’s programming similar to PROM
erasable programmable logic devices - EPLD
electrically erasable - EEPLD
design partitioned into macrocells
flip-flops used to make sequential circuits
software used to program interconnections to optimize use of hardware
input specified from schematics, truth tables, state graphs, VHDL code

54. EPLD Block Diagram
Primary inputs
Macrocell
Courtesy Altera Corp.

55. RAM based (volatile) FPGA’s
programming is fast and can be repeated many times
no high voltage needed
integration density is high
information lost when the power goes off

56. XILINX FPGA’s configurable logic blocks CLBs used
five input two output combinational blocks
two D flip flops are edge or level triggered
functionality and multiplexers controlled by RAM
RAM can be used as look-up table or a register file

57. XILINX FPGA’s

58. XILINX FPGA’s each cell connected to 4 neighbors
routing channels provide local or global connections
switching matrices(RAM controlled) are used for switching between channels

59. XILINX FPGA’s

60. XILINX FPGA’s (XC4025) 32 × 32 CLBs 25000 gates 422 k bites of RAM
operates at 250 MHz
32 kbit adder uses 62 CLBs

61. XILINX FPGA’s (XC4025)

62. Design synthesis

63. Circuit synthesis
derivation of the transistors schematics from logic functions complementary CMOS pass transistor dynamic DCVSL (differential cascode voltage switch logic)
transistor sizing performance modeling using RC equivalent circuits - layout generation
synthesis not popular due to designers reluctance

64. Logic synthesis
state transition diagrams, FSM, schematics, Boolean equations, truth tables, and HDL used
synthesis combinational or sequential multi level, PLA, or FPGA
logic optimization for area, speed , power technology mapping

65. Logic optimization Expresso - two level minimization tool (UCB)
state minimization and state encoding
MIS - multilevel logic synthesis (UCB)
Example :
S = (AB) Ci
Co= AB + ACi + BCi

66. Logic optimization Multilevel implementation of adder generated by
MIS II cell library from University of Mississippi

67. Architecture synthesis
behavioral or high level synthesis
optimizing translation e.g. pipelining
Cathedral and HYPER tools
HYPER tutorial and synthesis example:

68. Architecture synthesis example

69. Architecture synthesis

71. Vertical and Orthogonal CMOS COSMOS
Savas Kaya
Stack two MOSFETs under a common gate
Improve only hole mobility by using strained SiGe channel
pMOS transconductance equal to nMOS
Reduce parasitics due to wiring and isolating the sub-nets
COSMOS:
Complementary Orthogonal Stacked MOS
Conventional CMOS

72. Technology Base Strained Si/SiGe layers
Built-in strain traps more carriers and increases mobility
Equal+high electron and hole mobilities (Jung et al.,p.460,EDL’03)
SOI (silicon-on-Insulator) substrates
active areas on buried oxide (BOX) layer
Reduces unwanted DC leakage and AC parasitics
Cheng et al., p.L48, SST’04
Mizuno et al., p.988, TED’03

73. COSMOS Structure Single common gate: mid-gap metal or poly-SiGe
Ultra-thin channels: 2-6nm to control threshold/leakage
Strained Si1-xGex for holes (x0.3)
Strained or relaxed Si for electrons
Substrate: SOI

74. COSMOS Structure - 3D View I
Single gate stack: mid-gap metal or poly-SiGe
Must be engineered for a symmetric threshold
In units of mm

75. COSMOS Structure - 3D View II
Conventional self-aligned contacts
Doped S/D contacts: p- (blue) or n- (red) type
Inter-dependence between gate dimensions:

76. COSMOS Gate Control A single gate to control both channels
High-mobility strained Si1-xGex (x0.3) buried hole channel
High Ge% eliminates parallel conduction and improves mobility
Lowers the threshold voltage VT
Electrons are in a surface channel
Requires fine tuning for symmetric operation

77. 3D Characteristics: 40nm Device
Symmetric operation
No QM corrections
Lower VT
Features in sub-threshold operation
Related to p-i-n parasitic diode included in 3D

78. COSMOS Inverter No additional processing
Just isolate COSMOS layers and establish proper contacts
Significantly shorter output metallization
Top view
Peel-off top views

79. 40nm COSMOS NOT gate driving CL=1fF load
3D TCAD Verification
Inverter operation verified in 3D
40nm COSMOS NOT gate driving CL=1fF load

80. Applications Low power static CMOS: Area tight designs :
Should outperform conventional devices in terms of speed
Multiple input circuit example: NOR gate
Area tight designs :
FPGA, Sensing/testing, power etc. ?