1. Technion – Israel Institute of Technology Department of Electrical Engineering Winter 2009 Instructor Amit Berman Students Evgeny Hahamovich Yaakov Aharon JTool Jitter Analysis Tool Final Presentation

2. Agenda Motivation for Jitter Analysis Project Objectives System Overview JTool Block Diagram Blocks – Detailed  Zero Crossing and TIE Trend  Eye Diagram  TIE Filter  Histogram  Bathtub Curve & Linear Extrapolation  TIE FFT & Jitter separation 2 Jitter Calculation Calculation Example Results Comparison (JTool vs. Agilent’s EZJit+)  Modulated signal  Real Clock  Real Data Optional Next Steps Summary

3. Motivation for Jitter Analysis Increasing need for statistic signal analysis as a result of high speed data rates Saving test time by determining Jitter distribution for the long term from extrapolating short time measurements Helps minimize Jitter by finding Jitter components and sources Measuring and determining sampling margins Jitter analysis allows work with a unify system standards

4. Project Objectives Understanding Jitter analysis methodology and background Design and implement software for calculating Jitter parameters based on Agilent’s scope measurements Analyze Jitter for user created, pre-known pattern Analyze Jitter for high-speed printed circuit board Compare the method to other popular jitter measurement tools 4

5. System Overview Waveform Generator High-speed printed circuit board Agilent’s scope PC (JTool) 5 LinkLink to Equipment Parameters

6. Block Diagram Data Input *.csv format Zero Crossing TIE Jitter Trend Histogram Eye Diagram Bathtub Curve Jitter Extrapolation PDF CDF TJ@BER Jitter FFT PJ RMS DJ p-p Numerical Output Graphical Output Internal Function Initial Parameters TIE Filter Jitter Separation Conf. Level Shortening RJ RMS

7. JTool User interface Graphical User Interface implemented using “GUIDE” tool in MATLAB 7 JTool

8. JTool User interface 8 Initial Parameters entered by user Input sanity check included

9. Zero Crossing + TIE Trend TIE trend is created using zero crossing calculation and measuring the delta from the ideal clock 9

10. Eye Diagram The eye is constructed using the “eyediagram” function in Matlab 10 Eye diagram example with 11 eyes

11. TIE Filter Band Pass Filter from 10KHz to 245KHz (Flexible) Higher than 10KHz to eliminate wander phenomenawander Lower than 245KHz to eliminate spikes caused by sample accuracy and due to scope Bandwidth limitations 11 [KHz]

12. Histogram Histogram of the TIE Jitter is created 12

13. Bathtub Curve and Extrapolation Using the histogram we create PDF, CDF and a bathtub curve Some CDF samples are removed due to confident level Linear extrapolation is made 13 Removed

14. TIE FFT and Jitter Separation Jitter separation made at a freq. domain Using a threshold set by the code we separate RJ and PJ values 14 [Hz]

15. Jitter Calculation TJ@BER = 1UI – System Margin@BER 15

16. Calculation Example Sampled Waveform Extracted TIE Jitter 16 MHzMega Hz GSa/sGiga Samples per Second MptsMega Points

17. JTool Results 17 Back

18. Ezjit+ Results 18

19. Correlation on Modulated Waves JTool vs. Ezjit+ result comparison for modulated waves All results are at the same scale range Good TJ and PJ correlation to actual Jitter input and to Ezjit+ Both algorithms give mostly constant RJ as expected Partial correlation in DJ analysis, caused by TJ and RJ inaccuracies (DJ is extracted from TJ and RJ) 19 Ezjit+JTool DJ_p-pRJ_RMSPJ_RMSTJ@BER=10^-3DJ_p-pRJ_RMSPJ_RMSTJ@BER=10^-3 78.5nsec1.2nsec28nsec86nsec~05.6nsec0.6nsec25nsec Low Jitter 156nsec1.2nsec56nsec164nsec180nsec7.4nsec65nsec225nsecMedium Jitter 475nsec1.2nsec168nsec483nsecundef7.5nsec198nsecmore then UIHigh Jitter

20. Correlation on High Speed Boards Clock Pattern 1.35GHz clock pattern, Vp-p = 560mV, Vcm = 0V, Signal generated using Intel’s chip and board Signal captured using DSO91304A Agilent Scope (different model) Fsample = 40Gsa/s, 2Mpts samples taken 20 TIE P-P = 27 ps TIE P-P = 40 ps

21. Correlation on High Speed Boards Data Pattern 1.25GHz (2.5Gbits) data pattern, Vp-p = 1.2V, Vcm = 0V Signal generated using Intel’s chip and board Signal captured using DSO91304A Agilent Scope (different model) Fsample = 40Gsa/s, 2Mpts samples taken 21 TIE P-P = 163 ps TIE P-P = 170 ps

22. Optional Next Steps 1. Implement clock recovery algorithm based on the time samples Eliminate artificial spikes on the TIE trend – Improve results accuracy, especially p-p results Removes the need the LPF (no discontinuity of the TIE), perhaps still be needed for resolution granularity fix Remove need of user given freq. Or 1. Update the software to analyze the data based on a single voltage vector Save test time, mainly during the data acquisition part 2. Calculate TIE using created clock vector and not using modulo operator Remove spikes generated by wander Increase test time and code complexity Limits the algorithm to only clock testing (no data) 3. Set clear limit for BER cutting based on exact confidence level calculation (ref.11 and 12) Add confidence in measurement accuracy Increase algorithm efficiency by resolving unnecessary bits removal Increase the flexibility of the algorithm for different input types 4. Find accurate FFT separation threshold or improve separation algorithm Increase RJ – DJ separation accuracy Add "Pink Noise" awareness 5. Configuration of data analysis capability (partially implemented) Data patterns coverage 22

23. Summary JTool offers good measurement flexibility. Can serve as a foundation for future measurement development JTool is (mostly) an independent Jitter analysis tool Next steps should be implemented to increase algorithm’s robustness and quality

24. 24 Questions

25. Backup 25

26. Equipment Overview 26 Waveform Generator High-spee d printed circuit board Tabor Arbitrary Waveform Generator WW2571A Maximum frequency 100 MHz (Practical ~50MHz) Ability to create inner modulation High-speed printed circuit board With noticeable jitter

27. Equipment Overview 27 Agilent’s scope PC Agilent DSO80204B scope Bandwidth6 GHz Sample rate40 GSa/s Trigger jitter < 1 ps (RMS) EZJIT+Jitter & Timing Analysis Package PC which includes the JTool SW Back