1. Topic 4: Digital Circuits
(Integrated Circuits Technology)
Part two

2. Logic Levels: Practical Scenario
The two sets of levels are motivated by these scenarios
Scenario 1:
Source outputs logic high at lowest threshold, VOHMIN
Scenario 2:
Source outputs logic low at highest threshold, VOLMAX
A logic source output is modelled with a Thevenin model and a logic sink input is modelled as a resistive load.
For a worst case analysis, the resistive sink load is connected to ground in Scenario 1; the effect is to pull the input level below VIHMIN.
For a worst case analysis, the resistive sink load is connected to Vcc in Scenario 2; the effect is to pull the input level above VILMAX.
In Scenario 1:VOH = Vcc-IRTH, VIH = VOH – IRline
In Scenario 2:VOL = IRTH, VIL = VOL + I Rline
A source output voltage and sink input voltage will therefore decrease as current drain increases in the high state.
A source output voltage and a sink input voltage will therefore increase as current drain increases in the low state.
Define:
HIGH STATE NOISE MARGIN, NMHI := VOHMIN-VIHMIN
LOW STATE NOISE MARGIN, NMLO := VILMAX-VOLMAX
Larger margins  improved resilience to circuit nonidealities and interference

3. DC Loading
The output high and low limits are exceeded only if a device output is heavily loaded. Logic device loading is specified by
maximum current
Fanout := max. number of similar devices that can be connected to a load without exceeding high and low state current limits
Current Specs
IOHMAX
Max source current for which VOH  VOHMIN (valid output high)
IOLMAX
Max sink current for which VOL  VOLMAX (valid output low)
IIHMAX
Max input current for VIH  VIHMIN (valid input high)
IILMAX
Max input current for which VIL  VILMAX (valid input low)
Scenario 1: Output high connected to more than one sink. The current outputted by the source increases with the number of sinks.
Io = Iinj = nIin (for n similar sinks)
Scenario 2: Output low connected to more than one sink. Note that the current now flows into the output terminal (logic source becomes a current sink). Again current increases with the number of logic sinks.

4. DC Loading: Current specs
Scenario 1: Output high connected to more than one sink. The current outputted by the source increases with the number of sinks. Io = Iinj = nIin (for n similar sinks)
Scenario 2: Output low connected to more than one sink. Note that the current now flows into the output terminal (logic source becomes a current sink). Again current increases with the number of logic sinks. Io = Iinj = nIin (for n similar sinks)
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5. DC Loading: Fanout
Each gate input requires a certain amount of current to maintain it in the LOW state or in the HIGH state.
IIL and IIH
These are specified by the manufacturer.
Fanout calculation
Low state fanout, nFlow:= maximum number of similar gates that can be driven low so that Vo < VOLMAX
High state fanout, nFhigh:= maximum number of similar gates that can be driven high so that Vo > VOHMIN
Need to do current loading calculation for non-gate loads (LEDs, termination resistors, etc.)
E.g. What is the fanout of a 7400 which is required to drive several 74L00 devices?
Soln.: For the 7400 (driver), IOHMAX = -400A and IOLMAX=16mA. For the 74L00 (driven) IIHMAX = 10A and IILMAX = -0.18mA.
Thus
nFlow = |IOLMAX(source)/IILMAX (sink)| =16mA/0.18mA =88 (rounded to closest smaller integer)
nFhigh = |IOMAX(source)/IIHMAX(sink)| = 400 A/10 A = 40
From which nF= min(nFlow, nFhigh)=40.

6. AC Loading
All gate outputs have associated parasitic capacitances due to external wiring (including their gate pins) as well as internal semiconductor storage effects (junction capacitances). In addition there are parasitic capacitances associated with each gate input. Typically the capacitance component due to IC pins is of the order of 10-15pF.
The final transistor which drives the gate output acts as an electronically controlled switch with a pull-up to Vcc.
It is also important to note that in our switch model, LH > HL since, generally, r <<R. This also holds for electronic gates where the propagation delay from low to high (tPLH) is usually much greater than that from high to low (tPHL).
When one gate is driving several other gates the capacitive (AC) load is increased with each gate.
Cload = Total Capacitance
Co = Driver Output Capacitance
Ci = Input capacitance of each driven gate
CLOAD = CO +  Ci
As Cload increases so does the propagation delay, tp. This effect is also to be considered when a gate must drive long lines.

7. 3. CMOS Technology
Static complementary CMOS - except during switching, output connected to either VDD or GND via a low-resistance path
high noise margins
full rail to rail swing
VOH and VOL are at VDD and GND, respectively
low output impedance, high input impedance
no steady state path between VDD and GND (no static power consumption)
delay a function of load capacitance and transistor resistance
comparable rise and fall times (under the appropriate transistor sizing conditions)
Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes
simpler, faster gates
increased sensitivity to noise

8. 3.1. CMOS Circuit Topology
Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
pull-up: make a connection from VDD to F when F(In1,In2,…InN) = 1
In1
In2
PUN …
InN
F(In1,In2,…InN)
In1
NMOS transistors only
pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0
In2
PDN …
One and only one of the networks (PUN or PDN) is conducting in steady state (output node is always a low-impedance node in steady state)
Why PUN of PMOSs only and PDN of NMOSs only ? (Next slide)
InN
PUN and PDN are dual logic networks

9. b) Dual PUN and PDN PUN and PDN are dual networks
DeMorgan’s theorems
(A + B)’ = A’.B’
(A.B)’ = A’ + B’
a parallel connection of transistors in the PUN corresponds to a series connection of the PDN
Complementary gate is naturally inverting (NAND, NOR, NOT)
Number of transistors for an N-input logic gate is 2N

10. CMOS Complements

11. PDN
PUN

12. 3.2 Examples of CMOS Gates CMOS inverter VDD = 5V Vo Vi Vi Q1 Q2 Vo
0(L) OFF ON 5(H)
5(H) ON OFF 0(L) Q2
p-channel Vo Vi Q1
n-channel
Alternate symbols are used to represent MOS transistors., particularly for logic applications. This allows us to concentrate only on the logic state of the transistors in analysing CMOS circuits.
For all intents and purposes, transistor state is determined as follows: Q2
p-channel Vi Vo Q1
n-channel
CMOS inverter
Gate level
nmos
pmos
High ON
OFF
LOW

13. CMOS NAND Use 2n transistors for n-input gate
p-channel in parallel, n-channel in series
Add output inverter to convert to AND
Note increasing no. of NMOS xsistors => increasing resistance between Z and ground in output Low state => a higher low voltage

14. CMOS NOR Like NAND -- 2n transistors for n-input gate
p-channel series, n-channels in parallel

15. NAND vs NOR Result: NAND gates are preferred in CMOS. NAND NOR
For a given silicon area, PMOS transistors are have higher ON resistance than NMOS transistors => Output High voltage is lower due to series connection in NOR.
NAND
NOR
NAND output LOW voltage is not as badly compromised
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Result: NAND gates are preferred in CMOS.

16. CMOS characteristics
Essentially no DC current flow into MOS gate terminal
Gate has capacitance, C which MUST be charged then discharged for switching
Required power is CPDV2f ; where f is switching frequency, CPD is the power dissipation capacitance
Very little (0(nA)) current in output chain, except during switching when both transistors are partially on
More power required when signal rise times are small since transistors are on longer
Symmetric output structure ==> equally strong drive (IOH, IOL) in LOW and HIGH states
This is why..
Power dissipation in PCs increase with clock frequency
There is a lot of research on low voltage logic devices (5V, now 3.3V common)
Consider an inverter stage where the output oscillates at frequency f=1/tcyc. For a 0-1 transition at the output, the output must charge its load capacitance to VDD. The total energy drawn from the supply is used to charge the capacitor and is given by
This charge is via current drawn through the p-channel pullup transistor. For the next transition (from 1-0), the capacitor must discharge through the n-channel pull down transistor. The energy dissipated through the pulldown resistance is the same as above (conservation of energy). By symmetry, this must also be the energy dissipated in the pullup resistor for the 0-1 transition. So the total energy dissipated per cycle is 2E1 or
The average power is E/tcyc or
VDD
CPD

17. CMOS families and typical specifications
VOHMIN=VDD-0.1V, VIHMIN=0.7Vcc, VILMAX=0.3VDD, VOLMAX=0.1V
3V  VDD  18V (original 4000 family), 2V  VDD  6V (newer HC family)
Input source and leakage currents: <1A
Output current: typically 4mA but can be as high as 24mA
Families: original 4000 family (slower, lower power dissip.)
74FAMnnn: FAM = family type, nnn=function number – faster
54FAMnnn: same as 74FAMnnn but for military apps.
FAM : HC (High Speed CMOS), HCT (HC TTL compatible), VHC/VHCT (Very High speed), FCT/FCT-T(Fast CMOS TTL compatible/ with TTL VOH)
Egs: 74HC04 – hex inverter. IOLMAX=20  A, IOHMAX=-20A.
NB: Special handling precautions hold as CMOS can be damaged by very a small electrostatic discharge
4000 functions include: 4001 (2-input NOR), 4011 (Quad 2-input NAND)
Eg. The 74HC family has a quiescent power dissipation of 2.5W per gate, and CPD=24pF. Determine the power dissipation if VDD=5V, and the average switching frequency is 1MHz under
(a) No-load conditions
(b) When driving an IC with a 12pF input capacitance
Solution :
(a) With the total load capacitance as CPD, dynamic power dissipation is 24x10-12 x 52x 106 = 600W so the total is 602.5W.
(b) Now the total load capacitance is 24pF+12pF = 36pF; dynamic power dissipation is 36x10-12 x 52x 106 = 900W so the total is now 902.5W.

18. 4. TTL Diode Logic AND gate IN1 IN2 OUT L L L L H L H L L H H H
= Transistor-Transistor Logic. Uses bipolar transistors and diodes
Vcc
OUT
IN1
IN2 R
IN1 IN2 OUT
L L L
L H L
H L L
H H H
Diode Logic AND gate
Problem… defined levels change easily when loaded. E.g. when diode gates are cascaded. Need for transistor buffering
IN1 IN2 OUT
L L H
L H H
H L H
H H L
Vcc
IN1
IN2 R Vi
OUT R
NAND gate!
Schottky diodes have a forward drop of 0.25V. They are used to limit the saturation current when a bipolar transistor is turned ON. This allows for faster transistion from ON to OFF state which requires the removal of all charge in the transistor collector-base junction

19. TTL: practical realisation
Dynamic resistance: lower ON (L) voltage, faster switching
Limits current in transition
Diode AND gate
Totem Pole
Output
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Schottky
Diodes
Clamp diodes

20. TTL Logic families and specs
Vcc=5V±10%, Vohmin=2.7V, Vihmin=2.0V, Volmax=0.5V, Vilmax=0.8V
 NMh = 0.7V, NML=0.3V
Families: TTL e.g. 7404, 74H04, 74L04 original family
Schottky e.g. 74S04: faster, hi power consumption
Low Power Schottky e.g. 74LS04: lower Pd, Slower Schottky (common)
Advanced Schottky e.g. 74AS04 2x speed of S, same Pd
Adv. Low Pwr Sky e.g. 74ALS04
see table 3-11, Wakerly
For LS, typically: IILmax=-0.4mA, IIHmax=20uA, IOLmax=8mA, IOHmax=-400uA.
FANOUT (LSTTL into LSTTL)=20
NB: TTL outputs can sink more current than they can source.
74FAMnnn and 54FAMnnn TTL and CMOS devices have the same functionality. CMOS devices were given these designations following the wide success of the earlier TTL devices.

21. TTL vs CMOS TTL CMOS Noise Margins 0.3(high), 0.5 (low) 0.3Vcc
Input source currents
High in both states: 0.2 to 2mA(L), 20-50uA (H)
Typ < 1uA in both states
Power Consumption
Relatively high, fixed. 2mW for 74LS, 20mW for 74Sxx.
Depends on Vcc, frequency. Negligible static dissipation. Very low for FCTT
Output drive current
Asymmetric:
High state: 0.4-2mA
Low state: 8 – 20mA
Symmetric:
Typ 4mA but AC family can drive 24mA
Power supply voltage
5V ±10%
3V  Vcc  18V (original 4000 family), 2V  Vcc  6V (newer HC family)
Interconnection (CMOS to TTL, TTL to CMOS)
Cannot drive CMOS since VOHMIN(TTL)<VIHMIN(CMOS)
Pullup resistor needed unless using TTL compatible family e.g. HCT
Can directly drive TTL

22. Applications: CMOS/TTL interfacing
2.7
0.5
VOHMIN,
VOLMAX
VIHMIN,
VILMAX
3.5
1.5
CMOS
TTL
4.9
0.1
VOHMIN,
VOLMAX
VIHMIN,
VILMAX
2.0
0.8    
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23. 5. Applications: Unused inputs
Floating inputs can lead to unreliable operation!!!
Unused (Floating) Inputs [] Tie together and bundle with used inputs OR
[] Tie HIGH thru pull up resitor, Rpu OR
[] Tie LOW thru pull down resistor, Rpd
[] For CMOS use 1K-10K values
[] For TTL calculate based on # of inputs tied thru resistor so that:
Vcc-RpuIIHmax > VIHmin
RpdIILmax < VILmax
[]Too small Rpu makes TTL susceptible to spikes etc. over 5.5V.
See Sec , Wake.
Must ensure that does not affect design function. E.g. tie HIGH for AND/NAND or LOW for OR/NOR

24. Power supply filtering
For each logic IC place a small capacitor (0.01uF tp 0.1uF) across Vcc and ground in close proximity to the IC
Reduces transient effect of switching on power supply, particularly when supply source is connected via long circuit path (resistive and inductive effects). Essentially each capacitor provides a local reservoir for fast supply of charge required when the device switches
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25. Applications: Open-drain (CMOS) or open collector (TTL) outputs
In CMOS no PMOS transistor, use external pull-up resistor for Vcc drive
Vcc
Calculate external Rpu so that VOLMAX achieved at IOLMAX. Must include other loads so this gives minimum Rpu.
Vcc
Rpu IC Z
A B Q1 Q2 Z
0 0 open open 1
0 1 open ON 1
1 0 ON open 1
1 1 ON ON 0 A Q1 B Q2
Output stage of
Open Drain NAND

26. Why ? Slightly higher current capability
Can form an open-drain/collector bus. Can select data for access to common bus.. E.g for Dataout = Datai set Enablej =0, jI, Enablei =1,
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Problem -- really bad rise time due to all O/P capacitances in parallel and large pullup.

27. Applications: Bus Access - Contention and Tristate Logic
Common bus
Best “fix”….
Tristate logic
Vin EN
Vout 1 a 1 b ??
EN Vin Vout
0 x HiZ
1 1 0
1 0 1
“regular TTL or CMOS
Get bus contention when two outputs try to drive the bus to different states.
Value on the bus may be indeterminate;
Damage possible (a driving b!!)
On a PC data bus, can cause PC to crash
TRISTATE LOGIC is widely used in bus systems. They are particularly useful in computer systems where many loic devices must share common signal pathways. Memory devices such as EPROMs, RAMs etc have tristate logic built in, thus saving the user the task of adding external logic for bus control. The ENABLE lines of the internal tristate logic are usually tied to an external OUTPUT ENABLE or CHIP SELECT pin.
Available in inverting or non-inverting .. Sec Wakerly.
NO Pull-up needed
NO degradation in transition speed

28. Applications: Digital meets analog
Schmitt Trigger Inputs…Sec3.7.2/Wakerly
Schmitt trigger devices are used primarily to deal with signal levels which are not at valid logic levels. They can therefore be used for
interfacing noisy analogue signals to a logic circuit e.g. signals from switches, RC networks etc.
interfacing slow signals (i.e. signals which remain in the invalid range for relatively long periods)
regenerating degraded logic signals e.g. signals on a long serial communication line.
Schmitt trigger devices do comply with the input thresholds of the respective family. However, they employ a bit of hysterisis (memory!!) to take care of invalid signal levels. The devices are characterised by upper and lower thresholds (UT, LT). When the input exceeds UT it is treated as a logic 1 UNTIL it goes below LT. Then, and only then, is it treated as a logic 0. Vo
Exercise: Determine the outptuts for Vi as shown Vi VH VT VL VT VH Vi VL
Schmitt Trigger o/p Characteristic
Standard logic o/p Characteristic
Standard, VO
Schmitt, VO

29. VOL+VLED+(ILED*R)=VCC
Applications: Logic Drive
ILED is 10mA typically worst case
Use formula:
VOL+VLED+(ILED*R)=VCC
to determine R.
NB…….
Can assume worst case VOL=VOLMAX for some CMOS as well as TTL at IOL=ILED.
Best to use device for which IOLMAX>ILED.
Driving a LED with TTL
Logic Device
Vcc R
ILED
VLED
VOL
Low output turns LED ON
Drive current typ 5 -10mA
Use buffers for extra drive

30. Applications: Logic Drive
Driving a Solenoid or relay with TTL
5V relays do exist.
Some incorporate the free wheeling Diode.
Most have enough internal resistance to operate directly as shown.
Check using LED computation if built in resistance is sufficient or if an external series resitance is needed
Logic Device
Vcc
Free-wheeling
diode
protects
electronics
from coil
back emf
Low output turns activates relay or solenoid
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