1. First Paper in 1984 on FADCS FADC Cost Power RAM Power ECL TTL Narrow & Deep Need: Wide & Shallow More Expensive then FADC

2. Triple ADCs5 Xilinx FPGAs Lattice CPLDs 2 Xilinx EPROMs DRAM Delay Lines Analog SectionInfrastructure ADC Drivers 140 Mhz Voltage Regulators 5, 3.3,1.8 & -5

3. Analog Front End Delay Lines Delay Lines Buried in PCB

4. > 240 Channels are being used at BNL & PSI

5. Analog Input 0 to – 300 MV Delay = 2/3 OE Delay = 1/3 OE 16 x 1024 DP SRAM Delay = 0 OE WAR: 10 Bit Write Address Pointer F16 F0 A=2,6,10,14 RAR: 10 Bit Write Address Pointer F16 F0 A=1,5,9,13 10 Bit Adder 24Bit HD Test Register F16 F0 A=3,7,11,15 1024 - # 0f Steps Back (1 to 1024) DB Bus F25A0 Run Overflow FF Xilinx Block WFD Model 358D_PSI Yale University19 Sept 2002 5 AM Only for Testing @ Yale 16 x 1024 DP SRAM Triple 140 MHz ADC Offset Adjust AGS & RHIC Polarimeters WFD Perform CF Disc. & energy and make histograms in Xilinx Chip Write waveform samples in 64 Mbytes onboard SDRAM

6. TTL Clk Out NIM D AC Clk In Yes NO Model 358D- 200E 0 to 0.5 V DC Input Offset Adjust Clockwise More Positive NIM C Ch 1 Input Ch 2 Input Ch 4 Input Ch 3 Input Select DC Reference NIM Inputs Only 50 Ohm Input Range +/- 0.5 Vpp Front Panel NIM B NIM-TTL 10H125 OR Pin 1 140 MHz XTL Pin 3 171 - SPCLK3 - 12 170 – SPCLK4 - 13 79 – MCCLKEN- 40 CLK_ENB 169 – SPCLK5 - 14 EXT__IN T Stop Trigger ARM II Out 14  Sec 187 – CamCLK- 10 168 – SPCLK6 - 15 8 - GCKO–92 Virtex Load HD Register ADC Encode Clock Fanout SR8.ar ADC Run Yale University Top Level Schematic Model 358D_200E 14 Jan 2003 4:00 PM 172 – SPCLK2 - 11 Read Clk - XMHZ ARM I Out Read Clock XMHZ Out External 140 MHz ADC Clock Out SR4.ar Xilinx JTAG Lattice JTAG JTAG Back Panel EPROM Xilinx Load Mode 0G G 1 Stop Trigger 193 – !CamCLK- 9 8 To GCKO of Virtex Chips 1Volt PP Sinewaves TTL C TTL B TTL A

8. 1.4 W

10. 4 More Lemos ADCs Diff in / Diff Out WFD Model 361 : 8 Channel 10 bits @ 250 MHz Unchanged except for Clock

11. 1.RHIC Polarimeters 10 Mbytes/ sec for 4 Channel Module 2.Parallel bus systems can’t handle the rates 3.Look at serial systems 4.VITA34 Card size 8Ux220 mm Document in Draft Stage 5.Time Scale >2 year. R. Downing ( FASTBUS & VME for Physics) 6.ATCA (Advanced Telecom Computing Architecture) 7.8Ux280 mm 140 sq inch -48V Power 8.Switch Fabric: Mesh /Star/ Dual Star 9.Star: Each slot had 4x connection to the 2 Controller slots 10.Mesh: Peer – Peer connection 11.Xilinx: Yale has PCI Express IP Core & Demo Unit Current work

12. What is Next ? Need Larger PCB Size Mucho amounts of current @ 1.2 Volts and Lower Use Commodity Parts / Standards Serial Interconnect Very High Data Transmission on Copper Infiniband Standard: Clocking @ 2.5 GHz Embedded Clocking Cables 10 to 20 Meters

13. 1x Lane Consists of 2 Twisted pairs 20 inches on FR4 – 4 Layer PCB Next is x2 Higher 250 Mbytes/sec

14. ATCA Back Plane with Full Mesh 18 Layers: Dual Star 36 Layers: Full Mesh PER Slot: 4x Lanes: 1000 Mbytes/sec

15. Move Data Faster from the Front End to Computer Memory Embed PCI Express Silicon on Front End Copper Connections to @ 5 GHz and then11 GHz PCI Express Base (Need 1x) and not Infiniband (4x) Advanced Switching for Routing Event Data Trigger Processing Dual CPU sharing Memory Year 2006 Memory will be serial 32 Giga Bytes /sec Data Moving in Future !

16. STT-SLT Gigabit Ethernet Switch* GTT Farm* 12 Dual 1 GHZ PCs Event Builder Interface PC GSLT Interface PC 8 TP Links 2 TP – PCI Cards Preprocessor 1 PC Proposed Additions Current VME Crate CTD-SLT 8 TP Links MVD ADC Crates 4 TP – PCI Cards Preprocessor 1 PC VME Crate Preprocessor 1 PC Preprocessor 1 PC Preprocessor 1 PC Fast Ethernet Fig. 4 ZEUS Global Track Trigger (GTT) * Intel Grant Equipment Run Control* Quad 700MHz PC

17. Performance Availability Expandability, I/O, and Storage Serviceability 6 PCI slots (2 x PCIe, 2 x PCI-X, 2 x PCI (1 32/33 5v)) Single embedded Gigabit NIC Six 1” SATA or SCSI drives Optional CERC SATA, PERC 4e/SC, and PERC 4e/DC Remote management PCI card option Hot-plug hard drives (SATA OR SCSI) Memory: ECC Hot-plug, redundant power (optional) Optional add-in RAID Baseboard Management Controller (serial access) Internal tape Dual Intel® Xeon ® processors (Nocona) 64 Bit Extensions 800MHz Front Side Bus (Intel chipset) 256MB/12GB DDR2 SDRAM PCI-Express I/O Technology Rack (plastic)- bezel optional Tower (plastic) Key Messages  Intel Chipset at 800MHz  PCI-Express IO  HP HDs with hardware RAID  SATA HD and RAID  External Storage Key Messages  Intel Chipset at 800MHz  PCI-Express IO  HP HDs with hardware RAID  SATA HD and RAID  External Storage *Max memory at RTS is 8GB (until single-rank 2GB DIMMs 1H04 Nocona is 32/64 Dual Xeon: Memory address 36 Bits