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Micro controllers A self-contained system in which a processor, support, memory, and input/output (I/O) are all contained in a single package.

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Presentation on theme: "Micro controllers A self-contained system in which a processor, support, memory, and input/output (I/O) are all contained in a single package."— Presentation transcript:

1 Micro controllers A self-contained system in which a processor, support, memory, and input/output (I/O) are all contained in a single package.

2 Types of Microcontrollers Embeded (Self-contained) 8 bit 16-32 bit Digital Signal Processors

3 Basic Features Processor reset Device clocking Central processor Program and Variable Memory (RAM) I/O pins Instruction cycle timers

4 More Sophisticated Features Built-in monitor/debugger program Interrupt capability Analog I/O (PWM and variable dc I/O Serial I/O (synchronous, a synchronous) Parallel I/O (including direct interface to a master processor External memory interface

5 Processor Architecture CISC  Large amount of instructions each carrying out a different permutation of the same operation  Functionality of the instructions is more dependent upon the processor’s designer

6 Processor Architecture RISC  Fundamental set of instructions  More control for users to design their own operations

7 Processor Architecture Princeton (Van Neumann) architecture  Common memory for program and data  Simple chip design  Execution of an instruction can take multiple cycles

8 Processor Architecture Harvard architecture  Separate memory space program and data  Instructions are executed in one cycle  Easier timing of loops and delays

9 Processor Architecture Princeton architecture example Mov acc, reg Cycle 1Read instruction Cycle 2 Read data out of Ram and put into Acc

10 Processor Architecture Harvard architecture example Mov acc, reg Cycle 1Execute previous instruction Read “move acc, reg” Cycle 2 Execute “move acc, reg” instruction

11 Microchip PIC Micro controllers (PIC 16F877)

12 Hardware Architecture PIC Microcontrollers have following main features: Harvard Architecture RISC Feature CPU pipelines instruction fetching and execution in order to achieve an execution of one instruction at every cycle

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15 Memory Organization Program Memory Register File Memory

16 Program Memory Used for storing compiled code Each location is 14 bits long Every instruction is coded as a 14 bit word Addresses H’000’ and H’004’ are treated in a special way PC can address up to 8K addresses

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19 Register File Memory Consist of 2 Components  General Purpose Register (GPR) Files (RAM)  Special Purpose Register (SPR) files This portion of memory is separated into banks of 128 bytes long

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21 Register Addressing Modes There are 3 types of addressing modes in PIC  Immediate Addressing  Movlw H’0F’  Direct Addressing  Indirect Addressing

22 Direct Addressing Uses 7 bits of 14 bit instruction to identify a register file address 8 th and 9 th bit comes from RP0 and RP1 bits of STATUS register. Exp: ZequD’2’ btfssSTATUS, Z

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24 Indirect Addressing Full 8 bit register address is written the special function register FSR INDF is used to get the content of the address pointed by FSR Exp : A sample program to clear RAM locations H’20’ – H’2F’.

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26 Some CPU Registers STATUS PC W PCL PCLATH

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28 Instruction Set Every Instruction is coded in a 14 bit word Each instruction takes one cycle to execute Only 35 instructions to learn (RISC)

29 Instruction Set Uses 7 bits of 14 bit instruction to identify register file address For most instructions, W register is used as a source register The result of an operation can be stored back to the W register or back to source register

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31 Some Arithmetic Operations addwf FSR, w ; Add w to FSR and put result in w iorwf TMR0, f ; Inclusive OR w with TMR0 and store result in TMR0 addwf reg ; Add content of the reg to content of the w and store the result back into reg (source)


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