2. The domestic refrigerator-An example

3. A car door mechanism

4.  There are some sensors, some human interaction and a set of actuators that must respond to the requirements of the system.  One set of sensors relates to the door lock and another to the window. There are two actuators, the window motor and the lock actuator.  Central locking can be introduced or an alarm sounded if the door is not locked when the driver tries to pull away.  There is therefore considerable advantage in having a network which links the humble actions of the door control to other functions of the car.

5. Microchip and the PIC microcontroller  Background: The PIC was originally a design of the company General Instruments. The PIC was originally a design of the company General Instruments. It was intended for simple control applications, hence the name – Peripheral Interface Controller. It was intended for simple control applications, hence the name – Peripheral Interface Controller. The simple CPU was a RISC structure, with a single Working register and just 30 instructions. The simple CPU was a RISC structure, with a single Working register and just 30 instructions. General Instruments sold off its semiconductor division to a group of venture capitalists. MICROCHIP. General Instruments sold off its semiconductor division to a group of venture capitalists. MICROCHIP. Microchip made their development tools simple and low cost or free. Microchip made their development tools simple and low cost or free. Microchip stayed firmly entrenched in the 8-bit world. Microchip stayed firmly entrenched in the 8-bit world.

6. Choosing a PIC Microcontroller  The microcontrollers in the PIC10 through PIC14 families are considered low-end microcontrollers.  PIC microcontrollers in the PIC16 and PIC18 families are considered mid-level microcontrollers  16-bit PICs are considered high-end microcontrollers.

7. Choosing a PIC Microcontroller  Each PIC has unique features and subtle differences. The correct choice for your project depends on: Does the project require analog input or output? Does the project require analog input or output? Does the project require digital input or output? Does the project require digital input or output? How many I/O pins are required? How many I/O pins are required? Does the project require precise timing? Does the project require precise timing? How much memory does the project require? How much memory does the project require? Is serial I/O required? Is serial I/O required?

8. Harvard Architecture  A 14-bit wide program memory access bus fetches a 14- bit instruction in a single cycle.  This means that all locations are valid instructions.

9. Instruction Pipeline  The instruction pipeline is a two-stage pipeline which overlaps the fetch and execution of instructions.  The fetch of the instruction takes one T CY, while the execution takes another T CY.  However, due to the overlap of the fetch of current instruction and execution of previous instruction, an instruction is fetched and another instruction is executed every single T CY.

10. Instruction Pipeline

11. Orthogonal (Symmetric) Instructions  Orthogonal instructions make it possible to carry out any operation on any register using any addressing mode.  This symmetrical nature and lack of “special instructions” make programming simple yet efficient.  The mid-range instruction set uses only two non-register oriented instructions, which are used for two of the cores features. One is the SLEEP instruction which places the device into the lowest power use mode. One is the SLEEP instruction which places the device into the lowest power use mode. The other is the CLRWDT instruction which verifies the chip is operating properly by preventing the on-chip Watchdog Timer (WDT) from overflowing and resetting the device. The other is the CLRWDT instruction which verifies the chip is operating properly by preventing the on-chip Watchdog Timer (WDT) from overflowing and resetting the device.

12. Clocking Scheme/Instruction Cycle  The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3, and Q4.  Internally, the program counter (PC) is incremented every Q1, and the instruction is fetched from the program memory and latched into the instruction register in Q4.  The instruction is decoded and executed during the following Q1

15. Program Memory Organization  The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space.  The PIC16F877/876 devices have 8K x 14 words of FLASH program memory.  Accessing a location above the physically implemented address will cause a wraparound.  The RESET vector is at 0000h and the interrupt vector is at 0004h.