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Spartan-6 Memory Resources Basic FPGA Architecture
Xilinx Training
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Objectives After completing this module you will be able to…
Fully utilize the Spartan-6 distributed and block memory resources Understand the features and limitations of the Spartan-6 dedicated memory controller block (MCB) Use the Memory Interface Generator (MIG) to build your custom memory controller and design an appropriate interface to your off-chip memory component
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Every Design Uses Memory
Fast on-chip memory On-chip block RAM and ROM Frequently used for… Finite State Machines FIFO Large/local data storage External memory for larger data storage Dedicated Memory Controller Block (MCB) Supports evolving controller standards All memory solutions Must be fast and flexible Bitstream can pre-loaded with fixed data for a ROM or RAM Spartan-6 External memory
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Fast Memory Interfaces
Memory Options Distributed RAM/SRL32 Very granular, localized memory Minimal impact on logic routing Great for small FIFOs Fast Memory Interfaces On-chip Block RAM DRAM SDRAM DDR DDR3 FCRAM RLDRAM SRAM Sync SRAM DDR SRAM ZBT QDR FLASH EEPROM LOGIC DRAM SRAM FLASH EEPROM RAM / SRL 32 BRAM BRAM Spartan-6 Efficient, on-chip blocks Ideal for mid-sized buffering Cost-effective bulk storage Various memory controller cores For large memory requirements Memory Controller Block Granularity Capacity
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Interfacing to External Memories
DDR/DDR-II/DDR3 QDR/QDR-II RLDRAM FCRAM ZBT/NoBL FIFOs Dual-Ports CAMs Spartan-6 SDR SDRAM MCB supports many standards 1.5 V to 2.5 V Single or double data rate Different protocols High performance With advanced ChipSync™ technology This is the Select I/O functionality that enables the FPGA to be directly connected to memory specific I/O standards Besides having dedicated block RAMs, Spartan-6 also has other features that allow Xilinx FPGAs to lend themselves to memory interface applications. The Spartan-6 FPGA has a dedicated memory controller block that supports DDR3 and a few other standards. Note that the memory controller block in the Spartan-6 FPGA also supports the use of the ECC logic.
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Distributed RAM Distributed LUT memory
64-bit blocks throughout the FPGA available in 25% of the slices Single-port, dual-port, multi-port Can be used as 32-bit shift register Very fast (sub-nanosecond) Ideal for small and fast memories Coefficient storage Small data buffers Small state machines Small FIFOs Shift registers R A M Slice3 Logic Logic RAM Shift Register Not all LUTs support a distributed RAM option. This will depend on the type of LUT. Review the distributed RAM description in the Spartan-6 User Guide, for more information.
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Distributed RAM Features
Distributed LUT memory Can be loaded by configuration Synchronous (clocked) write operation But asynchronous (combinatorial) read Can make synchronous read when you use the neighboring flip-flop Easiest to build with the Core Generator Automatically builds the necessary input decode and output multiplexer logic Memories can be initialized Text I/O code in VHDL Coefficient file Or an initialization file placed in HDL code if inferring the memory R A M Slice3 Logic Logic RAM Shift Register
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Block RAM Features 18Kb Memory Multiple configuration options
True dual-port, simple dual-port, single-port Two independent ports address common data Individual address, clock, write enable, clock enable Independent widths for each port 300-MHz operation when using data pipeline option All operations are synchronous; all outputs are latched Data output has an optional internal pipeline register Faster clock rate, but increased latency Byte-write enable Enhances processor memory interfacing Load block RAM during configuration Reset during operation clears the registers, not the data content Do not violate address setup time while enabled Disable memory when address timing might be unpredictable This also saves power 18Kb Memory Dual-Port BRAM Note that even with the WE port disabled, if you violate the setup time, you can corrupt the memory even while reading. To avoid this, disable the EN port and make sure that the address and control signals are stable during operation.
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Spartan-6 FPGA Block RAM Block
Each block RAM block can be used as 18 Kb Block RAM 9 Kb Block RAM or 9 Kb Block RAM One 18 Kb Block RAM Two independent 9 Kb block RAMs
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True Dual-Port Block RAM
True dual-port flexibility Can perform read and write operations simultaneously and independently on port A and port B Each port has its own clock, enable, and write enable Every write also performs a read operation Read before write, write before read, or no output change Simultaneous read + write or write + write to the same location can cause data corruption Make sure that the address and control signals are stable during operation Block RAM configurations One block RAM: 16Kx1, 8Kx2, 4Kx4, 2Kx9, 1Kx18, 512x36 Or two independent 9K block RAMs: 8Kx1, 4Kx2, 2Kx4, 1Kx9, 512x18 Each port can have its own depth x width within that range 36 Wdata A Addr A Rdata A Port A Wdata B Addr B Rdata B Port B 18 Kb Memory Array
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Simple Dual-Port Block RAM
36 Wdata A Addr A Rdata A Port A Wdata B Addr B Rdata B Port B 18 Kb Memory Array One read port and one write port Natural structure for FIFOs Allows widest implementation 72-bit data width on 18K block RAM Up to a 72-bit read and write in one cycle 36-bit data width for 9K block RAM Doubles the memory bandwidth per block “Parity bits” are not dedicated for parity All byte-wide data has an extra ninth storage bit Can be used for parity or for any other purpose Parity generation / checking would need LUT logic
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Block RAM Configurations
Each 9 K 18 K True dual-port 8Kx1, 4Kx2, 2Kx4, 1Kx9, 512x18 16Kx1, 8Kx2, 4Kx4, 2Kx9, 1Kx18, 512x36 Two fully independent read and write operations Simple dual-port 8Kx1, 4Kx2, 2Kx4, 1Kx9, 512x18, 256x36 16Kx1, 8Kx2, 4Kx4, 2Kx9, 1Kx18, 512x36, 256x72 1 read & 1 write port Read AND write in 1 cycle Single-port 16Kx1, 8Kx2, 4Kx4, 2Kx9, 1Kx18, 512x36, 256x72 Read OR write in 1 cycle
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Byte-Wide Write Enable
Controls which byte is being written One write enable for each byte of data and its parity bit Useful when interfacing with processors a0 1001 ABCD AFFD FFFF clk address data we[3:0] output Byte-write operation during write-first mode Bytes not being written will show an undefined value on the output The output truly reflects the new memory content Writing always implies a read Be careful of reading when writing A write operation always implies a reading of data from the block RAM. Be careful reading data when writing to a block RAM, corruption is possible.
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Spartan-6 FPGA Memory Capacity
Spartan-6 Device Distr. RAM (Kb) Block RAM (Kb) 18-Kb Block RAM Blocks XC6SLX4 32 144 8 XC6SLX9 90 576 XC6SLX16 136 XC6SLX25 229 936 52 XC6SLX45 401 2,088 116 XC6SLX100 930 4,824 268 XC6SLX150 1,355 XC6SLX25T XC6SLX45T XC6SLX100T XC6SLX150T
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Memory Controller Block (MCB)
DDR DDR2 DDR3 LP DDR MCB Blk Spartan-6 has a New dedicated memory controller block Up to four controllers per device Saves between 500 and 2000 LUTs and registers versus a soft implementation Why a hard block? Very common design component Benefits of a hard block Higher performance: 800 Mbps Lower cost: smaller than soft logic Lower power: compared to soft logic Easy to design Abstracts away complexity of memory interfacing CORE Generator™ tool / MIG wizard and EDK support Interface Spartan-6 FPGA DDR3 SDRAM 800 Mbps* DDR2 SDRAM DDR SDRAM 400 Mbps* LP DDR *For all speed grades, except -1L
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MCB Features Memory support Memory Controller Block
DDR, DDR2, DDR3, LP DDR standards Simple, multi-port user interface Six 32-bit wide user ports Can be concatenated up to 128 bits Each port has 64-deep data FIFO and 4-deep command FIFO Simple… but also programmable Controller options Set user interface, calibration, addressing, and arbitration schemes Memory device options Control features and timing parameters Automatic calibration DQS centering DQ per-bit de-skew FPGA on-chip input termination Memory Controller Block Arbiter Controller PHY CMD FIFO 0 CMD FIFO 1 CMD FIFO 2 CMD FIFO 3 CMD FIFO 4 The MCB supports up to eight open banks for the DDR3 memory controller. CMD FIFO 5 Dedicated Routing 32-bit Bi-directional Data Path 32-bit Bi-directional 32-bit Uni-directional 32-bit Uni-directional 32-bit Uni-directional 32-bit Uni-directional
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MCB Options Number of memory controllers
2 for medium-sized devices, 4 for the two largest devices I/O interface to a single external DRAM device: 4, 8, or 16 bits wide Internal “user interface” bus width is programmable: 32 to 128 bits wide DRAM size DRAM bus width LP DDR DDR DDR2 DDR3 128Mb x16 x8 x4 256Mb 512Mb 1Gb 2Gb 4Gb LX9 LX4 M C B 3 M C B 1 LX45/T LX16 LX25/T M C B 3 M C B 1 M C B 3 M C B 1 M C B 3 M C B 1 LX100/T LX150/T M C B 4 M C B 5 M C B 4 M C B 5 M C B 3 M C B 1 M C B 3 M C B 1
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MCB Performance Higher data rates than with soft-core implementations
Memory Type Data Rate Max Theoretical Bandwidth per Memory Controller Interface Min Max 4-bit 8-bit 16-bit DDR TBD * 400 Mbps (200 MHz) 1.6 Gbps 3.2 Gbps 6.4 Gbps DDR2 800 Mbps (400 MHz) 12.8 Gbps DDR3 LPDDR Note, the Minimum frequency will be determined after characterization of the silicon. Higher data rates than with soft-core implementations Data rates up to 800 Mbps (DDR2, DDR3) Maximum theoretical bandwidth up to 12.8 Gbps Max values are for all speed grades in standard voltage devices
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Spartan-6 FPGA Memory Controller Block
Block Diagram Spartan-6 FPGA User Interface Calibration Module (RTL) IP Wrapper p0_cmd_clk p0_cmd_en Spartan-6 FPGA Memory Controller Block p0_cmd_bl p0_cmd_instr p0_cmd_addr CMD FIFO 0 CMD FIFO 1 Off-Chip Memory p0_cmd_full p0_cmd_empty CMD FIFO 2 Arbiter Controller CMD FIFO 3 CMD FIFO 4 mcbx_dram_clk mcbx_dram_clk CMD FIFO 5 mcbx_dram_clk_n mcbx_dram_clk_n mcbx_dram_cke mcbx_dram_cke p0_rd_clk mcbx_ mcbx_ dram_ras_n dram_ras_n P p0_rd_en I mcbx_ mcbx_ dram_cas_n dram_cas_n 32 - bit H O mcbx_dram_we_n mcbx_dram_we_n p0_rd_data mcbx_dram_odt mcbx_dram_odt p0_rd_empty Bi - directional I/O Clock Network Dedicated Routing Y B mcbx_dram_ddr3_rst mcbx_dram_ddr3_rst p0_rd_full p0_rd_full 32 - bit mcbx_dram_ba mcbx_dram_ba p0_rd_overflow p0_rd_overflow mcbx_dram_addr mcbx_dram_addr p0_rd_count p0_rd_count Bi - directional mcbx_dram_dq mcbx_dram_dq p0_rd_error p0_rd_error mcbx_dram_dqs mcbx_dram_dqs 32 - bit mcbx_dram_dqs_n mcbx_dram_dqs_n p0_wr_clk Uni - directional Data Path mcbx_dram_udm mcbx_dram_udm p0_wr_en 32 - bit mcbx_dram_ldm mcbx_dram_ldm p0_wr_data p0_wr_mask Uni - directional 32 - bit p0_wr_empty Uni - directional p0_wr_full 32 - bit p0_wr_underrun p0_wr_count p0_wr_count Uni - directional p0_wr_error p0_wr_error Simple user interface abstracts away complexity MIG / EDK wrapper delivers complete interface solution Internal block assembly and signal connectivity is transparent to the user
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Design Considerations
PLL creates two phases of MCB system clock SYSCLK_2X & SYSCLK_2X_180 Operate at 2X memory clock frequency Used for DDR I/O Divide by 2 in MCB creates memory clock frequency for other logic (1X clocks) Place MCBs on same side of device must share system clocks = same data rate MCB Block User Interface Controller Arbiter Data Path Memory Interface PHY Layer IOB User Clks 1X Clks : 2 : 2 PLL CLK CLK OUT0 SYSCLK_2X Clock Example: DDR2 800 Mbps 2X clk = 800 MHz 1X clk = 400 MHz CLK IN 2X Clks CLKB CLK OUT1 SYSCLK_2X_180 IO Clock Network IBUFDS FB BUFPLL_MCB User interface clocks Port clocks for command, write, and read path Asynchronous to system clocks FIFOs handle clock domain transfer 2nd MCB Block On the same side of device (Only in larger parts)
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Design Considerations
I/O pins for MCBs are predefined But are general-purpose I/O when a particular MCB is not used Package selection determines access to MCBs Higher pin count packages have more MCB blocks bonded out Migration across devices within same package Up or down one device density in most cases Applies only within a device family (LX or LXT, for example) The left and lower left MCB has the best migration path MCB pins shared less with other functions compared to right side
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Design Considerations
MCB blocks can be connected in parallel to create wider interfaces This will require extra CLB logic MCB blocks interface to a SINGLE memory device (x4, x8, or x16) There is No support for two x8 MC interfacing to a x16 memory Even for LPDDR, use an external VREF supply in the bank Supports soft calibration module input termination tuning Use a PLL nearest the center of the device to drive the BUFPLL_MCB
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Two MCB Design Flows For ISE® tool design flow For EDK design flow
Memory Interface Generator (MIG) wizard within the CORE Generator tool Best for non-embedded applications Simple GUI-driven tool for configuring MCB block Supports all MCB memory standards (DDR3, DDR2, DDR, LPDDR) For EDK design flow Multi Port Memory Controller (MPMC) Best for Embedded applications MCB block is underlying hardware implementation of the MPMC peripheral Simple GUI-driven tool within EDK / XPS
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Memory Interface Generator (MIG)
Easy to customize your memory controller and interface design Memory architecture, data rate, bus width CAS latency, burst length I/O bank assignments Generates RTL source code and UCF from hardware-verified IP Delivered as part of the ISE software (CORE Generator utility) MCB supports DDR, DDR2, DDR3, and LPDDR Soft Memory Controller supports other additional memory interfaces
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MIG Design Flow Open CORE Generator™
Integrate MIG .ucf constraints to overall design constraints file Run MIG, choose your memory parameters and generate rtl and ucf files Import RTL and build options into ISE project You can use the MIG to set your system and memory parameters. The tool generates the RTL and UCF files, which are the HDL code and constraints files. These files generated from a library of hardware-verified designs and your inputs are used to directly modify these files. The RTL code provided by the MIG is not encrypted and you have the flexibility to change and customize the RTL files. If you decide to make any code changes, you should perform additional simulations to verify your results. Synthesize design Customize MIG design Place and route design Integrate/customize MIG memory RTL testbench Timing simulation Perform functional simulation Verify in hardware Optional RTL customization
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MIG Enables you to customize your memory controller
Some options are specific to the memory controller standard (such as DDR2 and DDR3) Options for the physical layer and the FPGA controller Debug signals IOB options for power or speed MIG bank selection options Displays pins required Restricted I/O columns are disabled These screen shots are from MIG 3.0 for the DDR3 memory controller. You may recognize how similar the wizard is with the current MIG version.
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MIG Output Files UCF file folder RTL file folder
Pinout and clocking constraints Batch file (ise_flow.bat) with recommended build options RTL file folder Functional modules (physical layer, user interface, controller, testbench) Unencrypted for ease of customization Simulation file folder HDL simulation files including memory device models Synthesis files folder The MIG will generate these files and folders as in previous MIG versions. The UCF folder contains the UCF file along with a useful ise_flow.bat batch file. The batch file has the recommended build options for the ISE tool flow. It can be used as a guideline when you set your own ISE software options. The RTL folder contains the RTL files (as you can see from the screen shot). These are the modules mentioned earlier and includes the physical layer, user interface, controller state machine, and the testbench. The Simulation file folder contains the files necessary for the HDL simulation, including the memory device model. The Synthesis folder has the synthesis options for those who use Synplify.
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Summary Distributed LUT RAM Distributed LUT RAM Block RAM
Fast, localized memories Great for small FIFOs Block RAM Bigger on-chip memories Great for mid-sized buffering Dedicated Memory Controller (MCB) Fast connection to popular standard RAMs Memory controller cores Ideal for large memory requirements Memories can be built with the Core Generator or Memory Interface Generator (MIG) High-Performance Block RAM FPGA External Memory Interfacing
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Where Can I Learn More? User Guides Xilinx Education Services courses
Spartan-6 FPGA User Guide Describes the complete FPGA architecture, including distributed memory, block memory and the MCB Sparfan-6 FPGA Memory Controller User Guide Detailed description of all MCB functionality Xilinx Education Services courses Xilinx tools and architecture courses Hardware description language courses Basic FPGA architecture, Basic HDL Coding Techniques, and other Free videos!
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Trademark Information
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