1. J. Holma CLIC Workshop, Jan 30, 20131 J. Holma Acknowledgement M.J. Barnes CERN TE/ABT Present Status of Inductive Adder Development for the CLIC DR Extraction Kicker System

2. Overview  Specifications for CLIC Pre-Damping Ring (PDR) and Damping Ring (DR) Kickers  CLIC DR Kicker Pulse Definition  Challenges and Issues  Layout of the Kicker System with an Inductive Adder  Inductive Adder  Inductive Adder Design  Schematic of an Inductive Adder  Modulation schemes  Status of the Design  Schedule for Prototyping  Tests and Measurements of Prototype Adders J. Holma 2CLIC Workshop, Jan 30, 2013

3. (Selected) Key: DR  Damping Ring; PDR  Pre-Damping Ring. PDR & DR Kickers ( ): One injection and extraction system per ring and per beam (8 systems) Damping rings reduce beam emittance; hence kickers must be high stability (low ripple). Low beam coupling impedance is also required. CLIC General Layout J. Holma 3 CLIC Workshop, Jan 30, 2013

4. DR Kickers: Selected CLIC (2 GHz baseline), ILC & DAΦNE Parameters CLIC PDR CLIC DR ILCDAΦNE Beam energy (GeV)2.86 50.51 Total kick deflection angle (mrad)2.01.50.75 Aperture (mm)~402024 [6] (tapered)54.8 (tapered) Effective length (m)2*1.71.720*0.32=~6.40.94 Field rise time (ns)70010003~5 Field fall time (ns)70010003~5 Pulse flattop duration (ns)~160 NA Flattop reproducibility ± 1x10 -4 1x10 -3 ?? Flattop stability [inc. droop], (Inj.) per Kicker SYSTEM (Ext.) ± 2x10 -2 ± 2x10 -3 ± 2x10 -4 1x10 -4 ?? Field inhomogeneity (%) [CLIC: 3.5mm radius] [CLIC: 1mm radius] ±0.1 (Inj.) ±0.1 (Ext.) ±0.1 (Inj.) ±0.01(Ext.) ±?? ±3 (x=±27mm @y=0) ±10 (y=±10mm @x=0 Repetition rate (Hz)50 5 (3M burst)50 Pulse voltage per Stripline (kV)±17±12.5±5±5±45 Stripline pulse current [50 Ω load] (A)±340±250±100±900 J. Holma 4CLIC Workshop, Jan 30, 2013

5. M.J. Barnes & J. HolmaCLIC Workshop, Jan 30, 20135 CLIC DR Kicker Pulse Definition  Rise time: time needed to reach the required voltage (but includes settling time). 700-1000 ns allowed, less than 100 ns desired;  Settling time: time needed to damp oscillations to within specification;  Beam: 160 ns (for 2 GHz baseline, 900 ns for 1 GHz baseline) time window during which droop and oscillations must be within specification, however because of the kicker mismatch the pulse flattop may be required to be 310 ns (150 ns settling time);  Flattop stability: maximum of ±2x10 -4 for combined droop and ripple of DR extraction. This corresponds to ±2.5 V range for 12.5 kV output pulse for DR extraction;  Reproducibility: maximum difference allowed between any two pulses, ±1x10 -4 ;  Fall time: time for voltage to return to zero;  Minimizing rise and fall times reduces stress on kicker system.  To minimize settling time, impedance of system has to be well matched.

6. Challenges and Issues Se  ±0.02 % requirement for the pulse flattop stability for DR extraction kicker is an extremely demanding specification:  An order of magnitude better than in any existing systems  Active compensation of droop and ripple will be studied further with the prototype  Impedance mismatches  Suitable high precision measurements of the pulse in the laboratory J. Holma 6CLIC Workshop, Jan 30, 2013 ±0.02%

7. Kicker System with an Inductive Adder and a Stripline Kicker J. Holma 7CLIC Workshop, Jan 30, 2013 Schematic of kicker system with an inductive adder Even/Odd Mode Characteristic Impedance  Due to even/odd mode characteristic impedance optimization (See talk by C. Belver-Aguilar: CLIC DR Extraction Kicker Design, Manufacturing and Experimental Program), the impedance of the kicker striplines will not be 50 ohm as seen by the adder:  The even mode characteristic impedance (not pulsed, no virtual ground) is seen by the passing beam and this should be 50 ohm  The odd mode characteristic impedance (pulsed with different polarity pulses, virtual ground between striplines) is seen by the adder, 35-41 ohm. Therefore, the inductive adder will not be matched perfectly to the kicker striplines.  Settling time of the reflections will be ~150 ns, therefore the pulse flattop needs to be at least ~310 ns!  The prototype adders are designed for 1 µs pulse width Feedthru Ceramic Support Beam DAΦNE Striplines (Taken from: D. Alseni, LNF-INFN, “Fast RF Kicker Design”, April 23-25, 2008.)

8. Inductive Adder J. Holma 8CLIC Workshop, Jan 30, 2013 Inductive Adder  Solid-state switches;  Control electronics referenced to ground;  No electronics referenced to high voltage despite the high voltage output of the adder;  Modularity: the same design can potentially be used for DR and PDR kickers despite the different specifications. The PDR version will require more layers in series;  Redundancy and machine safety: if one switch or layer fails, the adder still gives a significant portion of the required output pulse;  Possibility to generate positive or negative output pulses with the same adder: the polarity of the pulse can be changed by grounding the other end of the output of the adder;  Source impedance is low, hence minimizing number of layers;  The output voltage can be modulated during the pulse. Schematic of an inductive adder Photo of an inductive adder

9. Operation Principle of an Analogue Modulation Layer M. Barnes, J. Holma 9CLIC Workshop, Jan 30, 2013  In analogue modulation layer, there is no energy storage capacitor but there is resistor R a  Resistor R a is effectively in series with the load  Load voltage: in which V max is the sum of the voltages over the layers except the analogue modulation layer, hence Vload ≤ Vmax.  Resistor Ra is in parallel with magnetizing inductance Lm  PASSIVE MODE: During the pulse, current through L m increases, which causes current through R a to decrease. Therefore, voltage over R a decreases, which causes V Load to increase. This voltage change is reverse in comparison with voltage droop caused by storage capacictors in other layers.  ACTIVE MODE: A linear switch provides a shunt path for the current trough resistor R a. Therefore, the voltage over R a can be controlled by controlling the current through the switch. No capacitor here Linear switch VaVa V Max V Load

10.  The analogue modulation layer can be used to generate:  a ramp function into output pulse to compensate droop (shown in blue)  an arbitrary waveform to compensate known ripple components (feed-forward control, shown in green) Operation Principle of an Analogue Modulation Layer (cont’d) J. Holma 10CLIC Workshop, Jan 30, 2013 VaVa V Max V Load with a compensating ramp with a sinusoid and ramp compensation ±0.02%

11. Status of the Inductive Adder Design  The main detail studies of the inductive adder have been completed, including mechanical design of the adder stack and electrical design of the printed circuit boards (PCBs)  The main components for the prototype adders have been ordered/received (pulse capacitors, transformer cores, semiconductor switches, gate drivers, high precision DC supply)  The mechanical parts have been designed, ordered and partly received (yesterday) for two 5-layer prototypes  The PCBs for the first 5-layer prototype will be layed out by CERN DEM in January-February 2013 and then manufactured. J. Holma 11CLIC Workshop, Jan 30, 2013 Mechanical design Ordering of components Electrical designSchematic and layout design of PCBs

12. Status of the Inductive Adder Design (cont’d)  A (prototype) terminating load for testing the prototype inductive adders and the striplines is presently being sort (one possible supplier is Barth Electronics). The specifications are 50 Ω, 12.5 kV, 150 W(average), bandwidth: DC…100 MHz. The 10 -4 stability of the load during 160 ns long pulse needs to be verified by testing.  On-going studies  Methodology to design the physical dimensions of the inductive adder structure so that its electrical parameters can be adjusted to meet the desired behaviour without several iteration steps.  FastHenry code has been used to compute the inductances of primary circuits of the inductive adder. The code will be used further to compute coupling capacitance and secondary leakage inductance of the adder stack.  The predictions will be verified with the first 5-layer prototype adder and, once verified, this approach can be used to design and fine-tune high performance pulse modulators in the future. J. Holma 12CLIC Workshop, Jan 30, 2013 Barth Electronics HV attenuator (resistor) FastHenry model of primary circuit of an inductive adder

13. Schedule for Prototyping and Testing  The first 5-layer prototype adder will be assembled in February/March 2013 and testing will be started immediately  Mechanical parts and the main components have been ordered and most of them have been delivered. The printed circuit boards will be manufactured in January/February.  A second 5-layer prototype is scheduled to be ready for testing shortly afterwards.  This adder is needed to test compensation/modulation methods as well as stability of adders in the bipolar setup. In a kicker setup with striplines, negative and positive voltage pulses are needed simultaneously.  The second prototype adder will be based on the updated design of the first prototype.  A full size 20-layer, 12.5 kV, 250 A, inductive adder will be built and tested in June- August 2013  The transformer cores and storage capacitors have already been ordered for this device. These components have the longest delivery times (~3 months)  Components for the second 20-layer inductive adder will be ordered during 2013.  The transformer cores and storage capacitors for this device have also been ordered.  The design can be updated, if necessary, according to tests with the first 20-layer prototype adder.  Tests with these two 12.5 kV, 250 A inductive adder and the striplines will start in 2014. J. Holma 13CLIC Workshop, Jan 30, 2013 Parts of the first prototype adder

14. Tests and Measurements of Prototype Inductive Adders Se Requirements:  Extremely flattop output pulse: 12.5 kV, 250 A, 160 ns with less than ±0.02 % (±2.5 V) of combined droop and ripple.  Reproducibility and stability: the difference of the waveforms of consecutive pulses has to be within ±0.01 % (±10 -4 ). Tests and Measurements to Demonstrate: New design methods for impedance modelling: 3D simulation of the inductive adder structure and printed circuit boards, to compute analytically the primary inductance, coupling capacitance and secondary inductance of the adder stack. To my knowledge, this is a novel, important and necessary step in achieving the required performance. New compensation methods: in order to reach the desired performance, analogue modulation (active and passive) will be applied to improve the output pulse using an analogue modulation layer in the inductive adder. Theoretical studies,whose results I have previously reported, show that this approach should be effective. These studies are valuable for gaining experience in designing pulse modulators with very high performance. The results of the studies will be published in conferences in 2013. The prototype DR kicker striplines will be tested and verified with the prototype inductive adders. J. Holma 14CLIC Workshop, Jan 30, 2013 Picoscope oscilloscope (12 bit, 100MHz) Bergoz current transformer Partial assembly of a prototype adder

15. Questions? J. HolmaCLIC Workshop, Jan 30, 201315 Comments?

16. References and Bibliography 1.Holma J., Barnes M.J.: “Sensitivity Analysis for the CLIC Damping Ring Inductive Adder”, accepted to be publ. in Proc. of Int. Power Modulators and High Voltage Conference, San Diego, CA, USA, Jun. 3-7, 2012. 2.Holma J., Barnes M.J.: “Evaluation of Components for the High Precision Inductive Adder for the CLIC Damping Rings”, Proc. of IPAC 2012, New Orleans, USA, May 20-26, 2012. 3.Holma J., Barnes M.J.: “Pulse Power Modulator Development for the CLIC Damping Ring Kickers”, CLIC-Note-938, CERN, Geneva, Switzerland, April 27, 2012. 4.Holma J., “Present Status of Development of DR Extraction Kicker System”, International Workshop on Future Linear Colliders, Granada, Spain, 26-30 Sept., 2011. 5.Holma J., Barnes M.J.: “Preliminary design of an inductive adder for CLIC damping rings”, Proc. of IPAC 2011, San Sebastián, Spain, 4-9 Sept., 2011. 6.Holma J., Barnes M.J., Ovaska S.: “Preliminary design of the pulse generator for the CLIC damping ring extraction system”, Proc. of 18 th IEEE International Pulsed Power Conference, Chicago, Illinois, USA, 19-23 Jun, 2011. J. Holma 16CLIC Workshop, Jan 30, 2013

17. EXTRA SLIDES J. Holma17

18. Modulation Schemes Se J. Holma 18 Digital modulation:refers to switching on and off a layer, whose capacitors are precharged to a predetermined voltage, during the output pulse. This is a ”coarse” method to modulate the output and cannot be used to compensate droop. However, turn-on of individual switches or layers may be initiated at different times to reduce ripple. Analogue modulation: a layer is used to compensate the droop of capacitors, significantly reducing the required capacitance per layer:  Passive analogue modulation: a layer works effectively as an R-L circuit. However there is no ability to change the modulation ”on-line”.  Active analogue modulation: a layer uses linear switches, and can be used to modulate the flattop during the pulse and provides the ability to change the modulation ”on-line”. Active analogue modulation requires linear semiconductor switches, therefore MOSFETs have been chosen as switches. PSpice simulations of the efect of the value of the capacitance per layer upon the flattop droop: (i) with no compensation, (ii) with RL- compensation and (iii) with active analogue modulation.

19. Double Kicker System: Concept (Extraction) J. Holma 19 KEK/ATF achieved a factor of 3.3 reduction in kick jitter angle, with respect to a single kicker, with single-bunch measurements. Extraction with one kicker magnet:  Requires a uniform and stable magnetic field pulse.  Two “identical” pulses are required;  One power supply sends the pulses to 2 “identical” kickers. Extraction with two kicker magnets:  1 st kicker system for beam extraction;  2 nd kicker system for compensation of jitter of deflection angle (ripple & droop) from 1 st kicker;  Figure shows 1 st and 2 nd kickers separated by a betatron phase of 2nπ: for a betatron phase of (2n−1)π the 2 nd kick is in the other direction. (Kicker) (Anti-Kicker) Time of flight

20. Example of Double Kicker System for DR Extraction In order that beam bunches and kicker field are synchronized in time at the 2 nd kicker system, the two kicker systems are powered in parallel. However, additional lengths of transmission line are required to compensate for the beam-of-flight between the 1 st and the 2 nd kickers. Potential problems  Different attenuation & dispersion of stripline waveforms (due to length of transmission lines);  Differences between magnetic characteristics of kicker & anti-kicker;  Imperfections in beam-line elements/alignment between kicker & anti-kicker. J. Holma 20  1 st kicker system (in damping ring) for beam extraction;  2 nd kicker system (in extraction line) for jitter compensation. Beam Time-of-Flight compensation.

21. 2-D Model of Stripline Kicker J. Holma 21

22. Operation Principle of an Analogue Modulation Layer M. Barnes, J. Holma 22  In analogue modulation layer, there is no energy storage capacitor but there is resistor R a  Resistor R a is effectively in series with the load  Load voltage: in which V max is the sum of the voltages over the layers except the analogue modulation layer, hence Vload ≤ Vmax.  Resistor Ra is in parallel with magnetizing inductance Lm  PASSIVE MODE: During the pulse, current through Lm increases, which causes current through Ra to decrease. Therefore, voltage over R a decreases, which causes V Load to increase. This voltage change is reverse in comparison with voltage droop caused by storage capacictors in other layers.  ACTIVE MODE: A linear switch provides a shunt path for the current trough resistor R a. Therefore, the voltage over R a can be controlled by controlling the current through the switch. No capacitor here Linear switch

23. Operation Principle of an Analogue Modulation Layer (cont’d) J. Holma 23 VaVa V max

24. Other Issues: Machine safety Se  If only one of the two striplines is powered, beam will receive ~1/2 deflection; high intensity beam could cause considerable damage to other equipment. This could result if a “single” switch were used for each stripline: an inductive adder (multiple primary switches) will help to avoid this problem.  Fast rise and fall times of field are desirable; e.g. if beam is mis-timed, with respect to the kick pulse, a fast rise/fall time will result in beam being swept faster across downstream materials/devices, minimizing potential damage. J. Holma 24

25. Contributors to Instability/Ripple & Droop Kicker System - Electrical Charging power supply (not expected to be a major contributor for “slow” charging of PFL); Pulse Forming Line (PFL) and transmission lines [attenuation and dispersion]; Switch (dynamic characteristic and temperature effects); Transmission line [attenuation and dispersion]; Feedthroughs (impedance mismatching) Terminating resistor (frequency dependence of value and temperature effects); Impedance matching of system. Others Long-term temperature effects (e.g. switches for LHC kicker dump generators ~0.2%/˚C ambient); Inhomogeneity of integrated field (integrated in beam direction); Although every effort will be made to minimise droop & ripple, it may be present at a level above that of the specification (±0.2% / ±0.02%). Hence, a novel pulse generator may be required as well as a double kicker system. Feedthroughs Schematic of one possible stripline kicker system J. Holma 25

26. The specifications for the pre-damping rings and the damping rings include:  low longitudinal and transverse beam coupling impedances;  high stability and reproducibility of the field;  excellent field homogeneity;  ultra-high vacuum. Feedthru Ceramic Support Taken from: D. Alseni, LNF-INFN, “Fast RF Kicker Design”, April 23-25, 2008. Beam Elliptical cross-section (increases deflection efficiency). DAΦNE Striplines (~0.9m) J. Holma26 Note: each taper ≈ 30% of overall length. Stripline structures will be used for the kicker element; CIEMAT & IFIC, in conjunction with CERN, are carrying out a complete optimization of the design of the DR striplines; Spanish Industry (TRINOS) will produce manufacturing drawings and a set of prototype DR striplines; The striplines will be supplied with suitable high voltage vacuum feedthroughs. Brief Summary of Stripline Design

27. Stripline Design: Longitudinal Impedance Longitudinal beam coupling impedance for untapered (Chao) and tapered stripline kicker (S. Smith, SLAC): Virtual Ground +ve -ve Beam pipe Ground Striplines driven to same magnitude, but opposite polarity, voltage, to extract beam. Total capacitance (C) is given by:  capacitance between a stripline and virtual ground  capacitance between a stripline and beam- pipe ground +/-ve Beam pipe Ground Beam Same polarity and magnitude of current / voltage induced on both striplines by beam. Capacitance (C) is given by:  capacitance between a stripline and beam-pipe ground Without dielectric or magnetic materials: 27 L ε R2011, October 3-5, 2011 M.J. Barnes