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HK & LVPS for EUSO –TA / -Balloon G. Medina-Tanco, L. Santiago, H. Silva Lopez, F. Trillaud, C. Lopez, J. Rojas, A. De la Cruz, S. Guerrero, G. Leon.

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Presentation on theme: "HK & LVPS for EUSO –TA / -Balloon G. Medina-Tanco, L. Santiago, H. Silva Lopez, F. Trillaud, C. Lopez, J. Rojas, A. De la Cruz, S. Guerrero, G. Leon."— Presentation transcript:

1 HK & LVPS for EUSO –TA / -Balloon G. Medina-Tanco, L. Santiago, H. Silva Lopez, F. Trillaud, C. Lopez, J. Rojas, A. De la Cruz, S. Guerrero, G. Leon

2 HK connections HOUSE KEEPING RS422 SPI High Level Command & Monitoring Signals Analog to Digital Conversion CPU RS422-RS232 converter SIREN CCB CLKB GPS PDMB HVPS SIREN [1 Open Drain output] 4 LVPS [4 Mon, 3 HL_Cmd] LENSES

3 HK connections HOUSE KEEPING RS422 SPI High Level Command & Monitoring Signals Analog to Digital Conversion CPU RS422-RS232 converter SIREN CCB CLKB GPS PDMB HVPS SIREN [1 Open Drain output] 4 LVPS [4 Mon, 3 HL_Cmd] LENSES Of course not needed in TA, but still available comm-channel if comm with TA or independent remote access is required Who turn HK on now? Anyway same protocol must be kept for HK On/Off.

4 HK Interfaces

5 HK module Individual boards’ functionality: PCB 05: LENSES, LVPS-PDM, LVPS-HK: (DC25-DB25). PCB 04: LVPS1-DP, LVPS2-DP: (DC37-DB25). PCB 03: SIREN-HK, CPU-HK, PDM-HK (DE9-DE9-DA15). PCB 02: CCB-HK, CLKB-HK: (DB25-DB25). PCB 01: POWER-HK, GPS-HK, HVPS-HK: (DE9-DA15-DA15).

6 HK module Back-lid (profile from Giuseppe’s module/CAD) produced @ CCADET-UNAM HK LVPS

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21 HK production status Two HK’s were produced Currently 3 students from UNAM are at Naples for HK+LVPS integration with DP Duration of mision 3 weeks Module casing: delay of 3 days at production  will arrive next week by DHL

22 HK module boards & Arduino

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24 HK Software

25 Software related to DP interfaces will be advanced during DP integration. HVPS we have a channel open & should not be a problem. PDMB there is nothing defined yet.

26 LVPS LVPS System: 4 boards implemented in 4 separate modules in DP rack Individual boards’ functionality: LVPS-PDM: PDMB[ON/OFF: HK] LVPS1-DP: CCB, CLK, GPS[ON/OFF: HK] LVPS2-DP: CPU (& DS) [ON/OFF: HK] LVPS-HK: HK[ON/OFF: SIREN] CURRENT Boards: input 28V NOT 110V But 110 V are AC not DC, yes? So, No-break/batteries in between ? WHO do this?

27 InterfacePower Consumption in W for Power Pack1 Power Consumption (changes) Power Consumption in W for Power Pack2 IR Camera 22 High Voltage Power Supply 22 LVPS DP13.3 LVPS DP24.2 Housekeeping66 LVPS-PDM3.5 LVPS-HK1.6 CPU12 CCB55 Data Storage88 GPS11 CLK33 PDMB (FPGA)7.28 PDMB-EC-ASIC10 Additional Spare 15 HeatersTBC Total 81.888.622 LVP consumption LVPS-PDM Current TA board does not work with PDM if those values for PDM are final But still the margin of tolerance must be confirmed because it is too low: < 2%

28 128.4 50.5 101.7 6.9 26.2 19.3 4.65 DB25 (HK_BOARD) DE9 (PWR_PDMB) CONNECTORS ON LVPS_PDM FRONT PANEL DE9 (BATTERY) 92.4 10 Dimensiones en mm Área efectiva enmarcada por línea azul 53.04 30.81 12.55 0.36 24.33 10.39

29 128.4 50.5 101.7 6.9 26.2 19.3 4.65 DB25 (HK_BOARD) DA15 (PWR_CPU) CONNECTORS ON LVPS2_DP FRONT PANEL DE9 (BATTERY) 92.4 10 Dimensiones en mm Área efectiva enmarcada por línea azul 12.55 39.14 0.36 6.22 24.33

30 128.4 50.5 101.7 6.9 26.2 19.3 4.65 CONNECTORS ON LVPS_HK FRONT PANEL 92.4 Dimensiones en mm DA15 (HK_ON/OFF) DE9 (BATTERY) 10 DE9 (HK_MON) DE9 (PWR_HKB) 10 Área efectiva enmarcada por línea azul 10.87 0.36 10.39

31 128.4 65.74 101.7 41.44 34.54 4.65 CONNECTORS ON LVPS1_DP FRONT PANEL 92.4 Dimensiones en mm DE9 (CCB) DE9 (CLKB) 6.9 DC37 (HK_BOARD) DE9 (BATTERY) DE9 (GPSR) Área efectiva enmarcada por línea azul 10 En esta opción se le agregaron lo de 3 divisiones = 5.08x3 = 15.24 69.32 30.81 12.55 0.94 16.19

32 128.4 55.58 101.7 6.9 31.28 24.38 4.65 CONNECTORS ON LVPS_HK FRONT PANEL 92.4 Dimensiones en mm DA15 (HK_ON/OFF) DE9 (BATTERY) 10 DE9 (HK_MON) DE9 (PWR_HKB) 10 Área efectiva enmarcada por línea azul 10.87 2.06 10.39 Agregar una subdivisión mas a los otros 3 submódulos sería otra opción = 50.5+5.08= 55.58 12.55 2.06 39.14 30.81

33 LVPS production status 1 LVPS set was produced

34 LVPS-PDM

35 PDM – Low Voltage Power Supply Board DC-DC of FPGA-PDM DC-DC of EC-ASIC Latching Relay of PDM Latching Relay of EC-ASIC DC-DC to power monitoring circuit Monitoring circuit (4 Operational amplifier built-in chip) Battery connector Power connector (to load) HK connector

36 HK – Low Voltage Power Supply Board Dual output DC-DC for ±12V-HK DC-DC for 3.3V-HKLatching Relay of 3.3-HK Latching Relay of 12V-HK DC-DC to power monitoring circuit Monitoring circuit (4 Operational amplifier built-in chip) Battery connector Power connector (to load) HK connector SIREN connector for Commands

37 DP – Low Voltage Power Supply Board #1 DC-DC for CCB DC-DC for GPSR Latching Relay of CCB Monitoring circuit (6 Operational amplifier TWO chips) Battery connector Power connectors (to load) HK connector To CCB To CLKB To GPSR Latching Relay of CLKB Latching Relay of GPSR DC-DC to power monitoring circuit DC-DC for CLKB

38 DP – Low Voltage Power Supply Board #2 DC-DC for CPU DC-DC for DTS Latching Relay of DST Latching Relay of CPU DC-DC to power monitoring circuit Monitoring circuit (4 Operational amplifier built-in chip) Battery connector Power connector (to load) HK connector


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