2. Parallel JPEG2000 Compression System Performed by: Dmitry Sezganov, Vitaly Spector Instructor: Stas Lapchev, Artyom Borzin

3. Abstract  High data rate due to rapid growth in imaging capacity.  Typical image data rates are several Gbits per second.  Solution – image compression.  Compression must be done prior to storage.  High compression ratio and performance is required.  Suitable compression algorithm should be used.

4. Abstract JPEG2000 Encoder JPEG2000 Decoder

5. JPEG vs. MPEG vs. JPEG2000 Figure 2. Decoded test image IRLS20: PSNR vs. BitRate for JPEG, JPEG2000 and MPEG4 VTC codec. Figure 3. JPEG2000 VM2.0 decoded test- image: PSNR vs. BitRate for entire image, background and ROI. JPEG2000MPEG2/4JPEG -Lossless compression Lossy compression YesNoYesStill images YesNo Large images Error resilience We choose JPEG2000 algorithm.

6. Comparison Compression Rate: 130:1 Wavelet (7KB, 5922 bytes) JPEG2000 JPEG (7KB, 6220 bytes)

7. ADV202 Overview Features of ADV202:  Single-Chip JPEG2000 Compression/Decompression cheap Solution.  Programmable Tile/Image Size.  Flexible pixel interface supporting 8, 10, 12, 14, 16-bit Y, Cr, Cb pixels.  Supports various interfaces (also DMA).

8. Satellite imagery 1m Pixel=1/4 m² 8.5km/s 2.5km 2.5km=5000pix

9. Requirements & Environment Project requirements:  Building multi-unit compression prototype system.  Easy extension.  Input bit rate is 1.2Gbps.  Fast HW implementation. Environment:  Virtex-II Pro Development Board  ADV202 JPEG2000 Video Codec  PC

10. Image tiling Input:  Data arrives line by line.  Input bit-rate 1.2Gbps  2 ADV202 devices.  5000 pixels width  2500 to each ADV202. 4096 5000 Tile#0Tile#1 Tile#2Tile#3 2500 Output:  Synchronization needed.  Coded stream is taken by pieces from each ADV202, strongly in order.

11. Architecture  Testing Unit – simulates high bit rate camera.  Channel#1 – Ethernet; Channel#2 – Rocket IO;  Initialize the Generator with a picture.  The Generator sends the picture periodically. Channel #1 Channel #2 1.2 Gbps Generator Compression Unit Testing Unit Raw stream Coded stream Coded stream and controls

12. Architecture PC Logic Memory Generator Codec PCB Loading image through Ethernet Duplicating and sending image through Rocket I/O channel Tiled image data Bus Data flow Testing Unit Compression Unit

13. Commands  Reset.  Read/Write ADV202 register.  Read/Write Codec Controller register.  Start TX.  Stop TX.  Resume TX.  Statistic commands. GUI interfaces our system through the following command:

14. Network Topology  Each command – packet.  Packet ID defines packet’s source and destination.  Load image (data for compression).  Command to PPC1 (from PC to PPC1).  Command to PPC2 (from PC to PPC2).  PPC1 to Controller (duplicated image stream).  Controller to PC (coded data).  PPC2 to PC (debug, statistics info). PowerPC1 PowerPC2 Controller

15. Software  PPC runs web server  Has IP address, standard capabilities like answering pings.  Can be reached from any computer on the local network.  Windows socket programming for Ethernet.  MFC – writing GUI.  When PPC accepts connection from PC – full duplex conversation.

16. PPC405 Processor Block Packet Processing Engine I/F Logic Rocket I/O Transceiver TX RX 16 64 ISBRAM 16 PLB Arbiter SDRAM Controller DCR Bus PLB PLB2OPB Bridge PLB BRAM Controller OPB Arbiter OPB LCD Controller GPIO Controller UART LITE PLB BRAM Ethernet Controller Testing Board Design To PC

17. PPC405 Processor Block Packet Processing Engine I/F Logic Rocket I/O Transceiver TX RX 16 64 ISBRAM 16 PLB Arbiter Codec Controller Module DCR Bus PLB PLB2OPB Bridge PLB BRAM Controller PLB BRAM OPB Arbiter OPB LCD Controller GPIO Controller UART LITE Interrupt Controller Compression Board Design To Codecs

18. Codec Controller Design Soft RESET Bus Interconnect Logic Rocket IO Interface CPU Interrupt Controller 64 bit PLB Bus Rocket IO Packet Processing Module FIFO In FIFO Out ADV202 PCB 36 ResetBlockResetBlock 32 ModeBlockModeBlock DCR Multiplexing Logic ispGDX240AV Crosspoint Device 36 Hard RESET Our logic. Hardcore. Softcore.

19. Extension and Scalability Soft RESET Bus Interconnect Logic Rocket IO Interface CPU Interrupt Controller 64 bit PLB Bus Rocket IO Packet Processing Module FIFO In FIFO Out ADV202 PCB 36 ResetBlockResetBlock 32 ModeBlockModeBlock DCR Multiplexing Logic ispGDX240AV Crosspoint Device 36 Hard RESET  Faster channel needed.  Minimal extension by 2500 pixels.  Recommended extension by 5000.

20. RIO Processing Module  Round-robin arbitration.  Priority on transaction duration by predefined settings.  Clock frequency is 1/2 of PLB clock. Bus Core Interconnect Logic Packet Requesting Generator StartRD Packet Sending Controller Local Bus Grant_0 Grant_1Grant_2 Packet Starting TX Grant_3 StartTX RioRDY FIFO_inFIFO_out Packet Retrieving Controller

21. Codec Controller - FIFO  Each FIFO block = 1 BRAM(18Kbit).  9KBytes per ADV202.  Different clocks on both sides. FIFO 512 X 36 36 clock_in fifo_gsr_in write_en_in read_en_in full_out empty_out read_data_out fifostatus_out write_data_in 36 4 read_clock_in JP1 FIFO_in JP2 FIFO_in FIFO Write interface 36 FIFO Read interface 36 FIFO1 512 X 36 FIFO2 512 X 36 FIFO3 512 X 36 FIFO4 512 X 36 FIFO Write interface 36 FIFO Read interface 36

22.  Codec PCB is a daughter card - P160 connector must be mounted.  2 ADV202 units to sustain required data rate.  2 X 76 ADV signals vs. only 109 P160 available pins.  Apply Switching Logic to achieve max flexibility.  PCB must meet 3 tests requirements ( SEU, Latch Up, Total Dose ).  Appropriate connection to signals must be implemented for debug purposes - Mictor. PCB Design Considerations

23. Switching Logic Requirements  Multiple interfaces and Operation modes – Signal switching ( static Signal rerouting )  Bi directional signals – signal direction switching ( dynamic )  ADV202 Share signals – 1 to 2 signal routing.  Single ADV202 clock – combinatorial logic, uniform signal propagation.  Some signals are not routed through the switching logic ( clocks, essential signals )  Fixed High or Low Output.  106 P160 + 62 X 2 ADV202 signals – minimum 230 switching logic I/O pins

24. ispGDX240 Overview  240 I/O, “Any Input to Any Output” Routing  Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation  4.5ns Input-to-Output delay  3.3V Core Power Supply  240 I/O pins

25. ADV202 Signal Routing ispGDX240VA VirtexVirtex 46 60 62 60 49 3 VClk, Mclk, Rst 62 P160

26. Orcad

27. PCB Features  Devices: 2 ADV202, ispGDX240, Voltage Monitor.  Connectors: P160 ( JX1 & JX2 ), ispGDX JTAG port.  Header: external power supply and Reset.  Debug capabilities:  4 Mictor connectors ( 32 signals each ) – Logic Analyzer.  Power supply voltage LED indicators.  Reset push button.  Test points: Ground and Vcc.  Pads for clock probing.

28.  The 3 tests are:  SEU – full work under radiation.  Latch Up – minimal operation, supply current.  Total Dose – radiation, full functionality test.  Each ADV202 must be placed in a socket ( all boards ).  All mounted components must be at least 0.5 cm far from the ADV202.  SEU - no special Codec PCB design requirements. Tests Requirements

29.  Latch-Up:  Only one ADV202 is mounted.  No capacitors bigger than 0.1uF mounted.  Connectors for external power supply must be present.  External reset signal + reset on power up.  All signals will be connected to static values.  External clock signal.

30. Total Dose Requirements  Total Dose:  All inputs tied high trough a pull up resistor.  No active components present.  Stand alone – all essential control signals are external.  Five ADV202 are mounted.  All outputs connected to half Vdd through voltage division resistors.  2 different ORCAD schematics:  SEU + Functionality.  Latch-up + Total Loss ( mounted differently ).

31. Current Status  Finished design of the Codec Board, Codec Board ORCAD Schematic.  Finished integrating Ethernet controller, writing web server application.  Writing GUI client which connects PPC1, capable of sending and receiving data – full duplex communication.  Establishing Rocket IO connection – almost finished.  Controller top design.

32. Future Plans  PCB layout – 4 weeks.  PCB manufacturing and testing – 6 weeks.  ORCAD for Latch-up and Total Dose PCB – 1 week. In parallel:  Controller implementation + loopback – 6 weeks.  Controller and PCB integration – 4 weeks.  Establish real 1.2Gbps input stream – 6 weeks.  Enhance GUI application for supporting full functionality – 2 weeks.