1. [M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 06 Overall Project Objective : Dynamic Control The Traffic Lights

2. Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates (Refined)  Floorplanning (Refined)  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

3. Traffic Flows Sensors (Blue) To detect the car entered Sensors (Red) To detect the car leaved ARM 1 ARM 2

4. Traffic Light Flow Whenever pedestrian push the button, then this light will insert in the end of this cycle. ARM 1 ARM 2 Red GreenY Green (S traight + R ight )YRed+Green(L eft ) Red Y Green (S traight + R ight )YRed+Green(L eft )Y Phase A Phase C Phase BPhase APhase B ARM1 ARM2 PED We define three phases (A,B,C) for different operations.

5. SW – Switch light G – Green R – Red Y – Yellow T – Time for Yellow PED – Pedestrian SW (1bit) ARM (1bit) PED(1bit) CLK ARM1 [1:0] FSM Initial G.R Y.R R+L eft.R Y.R R.G R.Y R.R+L eft PED SW = 0 SW = 1 T < 2 T = 2 SW = 1 SW =0 T<10 PED = 1 T = 2 PED = 1 T = 2 T<= 2 SW = 0 T=15 T = 2 PED = 0 T = 2 PED = 0 ARM = 0ARM = 1 FSM For Lights Clear (1bit) ARM2 [1:0] PED(1bits) Blink T=10 T < 5 Complete(1bits)

6. Hold until n 1 or n 2 changes Light favors n 1 or n 2 ? n1n1 n2n2 T<r 1 ? T<r 2 ? T>= R 1 ?T>= R 2 ? n 1 =0? n 2 =0? f 1 <=0? f 2 <=0? Switch Light Reset T = 0 No Yes No Yes No Light favors arm 1 or arm 2 ? n1n1 n2n2 T<r left ? T>= R left ? No Yes No Yes No n 1 not change in T = 5? No Control reset Pedestrian For Green light For Red + Left T>= R p ? Yes No For Pedestrian n 2 not change in T = 5? n 1, n 2 :# of cars T :Time spent in this phase R i, r i : Max. and Min. time for each phase f i : the control function f 1 = α 1 *n 1 + β 1 – n 2 f 2 = α 2 *n 2 + β 2 – n 1

7.  Structure Verilog is basically done. There are nine essential modules in total.  Transistor count increases dramatically because of an additional block for implementing “repeat” in behavioral modeling. Light control FSM

8. Structure for Light control FSM D-FFs Combinational logic for next state Decoder Encoder next state [3:0] current state [3:0] Combinational logic for output Arm1 [1:0] Arm2 [1:0] PEDESTRIAN complete SW arm PED delay Delay signal generator CLK Y2R, PEDBLINK etc. Need to re-allocate blocks for better floor plan since we’ve known precise transistor count. T: 48 T: 36 T: 150 T: 140 T: 80 T: 352

9. Floor plan for Light control FSM Decoder T: 140 D_FFs T: 80 Combinational logic for next state T: 150 Encoder T: 48 Sel,Reset, Complete T: 36 Output T: 36 Mux T: 144 Comparator T: 120 Counter T: 88 clk Output: Arm1 Arm2 PEDESTRIAN Complete Process for state Process for output Input: arm SW PED Since it is separated into nine blocks, it is flexible to fit the chip’s floor plan. This FSM’s floor plan can be decided after other blocks are done.

10. `include "gates.v" `include "lib.v" module decoder(s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, state); input [3:0] state; output s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10; wire c0_1, c0_2, c1_1, c1_2, c2_1, c2_2, c3_1, c3_2, c4_1, c4_2, c5_1, c5_2, c6_1, c6_2, c7_1, c7_2, c8_1, c8_2, c9_1, c9_2, c10_1,c10_2; wire [3:0] state_b; NOT inv1(state_b[0], state[0]); NOT inv2(state_b[1], state[1]); NOT inv3(state_b[2], state[2]); NOT inv4(state_b[3], state[3]); //encoder for s0 NAND2 s0_1(c0_1, state_b[0], state_b[1]); NAND2 s0_2(c0_2, state_b[2], state_b[3]); NOR2 s0_3(s0, c0_1, c0_2); //encoder for s1 NAND2 s1_1(c1_1, state[0], state_b[1]); NAND2 s1_2(c1_2, state_b[2], state_b[3]); NOR2 s1_3(s1, c1_1, c1_2); //encoder for s2 NAND2 s2_1(c2_1, state_b[0], state[1]); NAND2 s2_2(c2_2, state_b[2], state_b[3]); NOR2 s2_3(s2, c2_1, c2_2); //encoder for s3 NAND2 s3_1(c3_1, state[0], state[1]); NAND2 s3_2(c3_2, state_b[2], state_b[3]); NOR2 s3_3(s3, c3_1, c3_2); //encoder for s4 NAND2 s4_1(c4_1, state_b[0], state_b[1]); NAND2 s4_2(c4_2, state[2], state_b[3]); NOR2 s4_3(s4, c4_1, c4_2); //encoder for s5 NAND2 s5_1(c5_1, state[0], state_b[1]); NAND2 s5_2(c5_2, state[2], state_b[3]); NOR2 s5_3(s5, c5_1, c5_2); //encoder for s6 NAND2 s6_1(c6_1, state_b[0], state[1]); NAND2 s6_2(c6_2, state[2], state_b[3]); NOR2 s6_3(s6, c6_1, c6_2); //encoder for s7 NAND2 s7_1(c7_1, state[0], state[1]); NAND2 s7_2(c7_2, state[2], state_b[3]); NOR2 s7_3(s7, c7_1, c7_2); //encoder for s8 NAND2 s8_1(c8_1, state_b[0], state_b[1]); NAND2 s8_2(c8_2, state_b[2], state[3]); NOR2 s8_3(s8, c8_1, c8_2); //encoder for s9 NAND2 s9_1(c9_1, state[0], state_b[1]); NAND2 s9_2(c9_2, state_b[2], state[3]); NOR2 s9_3(s9, c9_1, c9_2); //encoder for s10 NAND2 s10_1(c10_1, state_b[0], state[1]); NAND2 s10_2(c10_2, state_b[2], state[3]); NOR2 s10_3(s10, c10_1, c10_2); endmodule module combi_next_state(out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, arm, SW, PED, delay); output out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10; input s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, arm, SW, PED, delay; wire arm_b, SW_b, PED_b, delay_b, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15, w16, w17, w18; NOT inv1(arm_b, arm); NOT inv2(SW_b, SW); NOT inv3(PED_b, PED); NOT inv4(delay_b, delay); AND2 a1(w1, delay, PED_b); AND2 a2(w2, delay, PED); NAND2 n1(w7, s4, w1); NAND2 n2(w9, s4,w2); NAND2 n3(w5, s8, w1); NAND2 n4(w10, s8, w2); NAND2 n5(w3, s0, arm_b); NAND2 n6(w4, s1, SW_b); NAND2 n7(w6, s0, arm); NAND2 n8(w8, s5, SW_b); Structure Verilog for Decoder and Combinational Logic (partial)

11. The result shows that the FSM can function properly through three inputs and then generate corresponding outputs and states. Future work: Go down to transistor level and revise the floor plan. The simulation result

12. Block Diagram

13. Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

14. Block (# used)Transistor Counts Register ( 13 )6804 MUX ( 12 )9300 Accumulator ( 4 )1848 ALU ( 1 )4848 Comparator 8-bits ( 1 )240 Flow Control FSM832 Light Control FSM882 ROM~0 Other- Total24754 Transistor Counts Estimates

15. Block (# used)Transistor CountsSize Estimates (um) Register ( 13 )680425792.6 MUX ( 12 )930035254.4 Accumulator ( 4 )18487005.4 ALU ( 1 )484818377.8 Comparator 8-bits ( 1 )240909.8 Flow Control FSM8322790.0 Light Control FSM8822957.7 ROM~00 Other Total~ 24754~ 93087.3 Block Size Estimates

16. Register (1bit) 2X1 MUX Estimate Block Size From Layout : 16.6 6.6 13.5 6.5 BlocksSize Estimates ( um ) 2:1 MUX (1bit)87.75 8:1 MUX (1bit)614.25 16:1 MUX (1bit)1316.25 12-bit Register1314.72 11-bit Register1205.16 8-bit Register876.48 Accumulator (8-bit) 1560.4 = 34.4 x 45.36 Accumulator (11-bit) 2950.1 = 47.3 x 62.37 Light Control FSM2957.7 * Flow Control FSM2790.0 * ALU 19177.6 = 96.94 x 197.83 From equation, we obtain 18377 um^2 Comparator200 Asterisk(*) : no precise layout outline now. Some Basic Layout Ratio:

17. Transistor Counts T:154 X 2T:308 X 2 T:154 X 2T:308 X 2 T:132 X 2T:154 X 2 T: 96 X 8T:896 T:96T:154 T:112T:308 T:112T:308 T: 672 T: 96 T: 1540 X 2 T: 12 T: 1320 T: 1980 X 2 T: 1980 T: 1526T: 4848 T: 132 T: 240 T: 882T: 832

18. Area Estimates on Each Block 29501205 29501205 876 x 8 88 x 64 88 x11 1205 1560 876 1205 x 10 88 88 x 110 1316 x 11 97 x 198 1316 x 11 1206 x 10 88x11 614 x 8 88 x 8200 2790 2957

19. Expected Size on Each Block 55x65100x13 55x65100x13 13x100 133x52 88 x 64 19.5x54 13x10 47x35 14x67 100x130 13.5x6.5 135x71.5 143x108 97 x 198 131x101 13x81 108x52 54x2045x45 60x60 65x65 19.5x54 14x67 143x108

21. 11 2211 110 220 110 11 6611 176 11 121 11 22 12 111 64 8 11 88 88 8 16 1 27 8 5 6 Wire Space

22.  M1, M2  Local connect  VSS & VDD  M3,M4  System Clock  Global Routing  Control Signals Metal Directionality

23. Question ?

26. User Input Q User Input R,r AccumReg 1 11 ENTER 11 AccumReg 11 OUT / LEFT s0,s1: X 2 q0,q1: X 2 Reg X 10 11 Reg X 10 2:1 MUX 110 11 X 10 11 X 9 11 X 1 q0 q1 11 β n1 n0 11 Q_len11 16:1 MUX 4 Sel 11 s0 s111 Sel 4 N_avg αn 0 -n 1 αn 0 q 0 -s 0 q 1 -s 1 α0α0 α1α1 Q(αn 0 -n 1 ) ALU 2 Sel_ALU 1:16 De-MUX 4 Sel 12111 Reg X 9 12 bit Reg X1 11 bit n0 n1 ROM 11 β 2:1 MUX 12 n_avg Q(αn 0 -n 1 ) q 1 -s 1 q 0 -s 0 αn 0 αn 0 -n 1 11 F α 0,α 1: X 2 ROM Reg 8X8 11 8 X 8 : Dot Line to Comparator R,r, RL,rl for Arm1 Arm2 11 ½ 2:1 MUX Dot Lint to FSM β 8 X 8 2 : 1 MUX INT. Compar 1 FSM SW ARM CLK Clear FSM 1 Complete ARM 1 ARM 2 PED1 2 2 ½ 11 ROM 11 User Input 2:1 MUX Reg 11 Accmu 8 1 Clk Div. 8 Accmu 1 Left-Turn Counter T 8 8 8 Reg 8 8 8 8 System Clock 1 PED 1 1 1 1 1 R & r, R_L& r_L Sel_C Ser_D 3 1 4X3 3 2 Sel_ALU Sel_C Sel ARM n 0 = 0 n 1 = 0 F <= 0 8 : 1 MUX n0n0 n1n1 F 1 Sel_D System Clock Trigger, when cars go left turn ARM 1 11 1 Shifting 1