1. Traffic light contoller using FSM

2. Traffic Light Controller - Specification
Main Highway has higher priority and the signal remains green on default
Occasionally cars arrive on country road. A signal X becomes 1 when there is a car on the country road.
When there is a car the country road traffic light should just turn green long enough to let the car pass after which the signal turns yellow and then red and highway light turns green again

3. Traffic Light controller – State Graph

4. Traffic Light Controller - States
S0: Hwy : Green , Country : Red S1: Hwy : Yellow , Country : Red S2: Hwy : Red, Country : Red S3: Hwy : Red , Country : Green S4: Hwy : Red , Country : Yellow

5. Traffic Light Controller - Verilog Code
`define S0 3’b000 `define S1 3’b001 `define S2 3’b010 `define S3 3’b011 `define S4 3’b100 `define GREEN 3’b001 `define RED 3’b010 `define YELLOW 3’b011 module traffic_light (X, clk, reset, hwy, country); input X, clk, reset; output[1:0] hwy, country; reg[2:0] state, next_state;

6. Traffic Light Controller – Verilog Code
// Next State Logic (X or state or reset) begin if(reset ==0) next_state =0; else case(state) S0: begin if(X==1) next_state = S1; else next_state = S0; end S1: next_state = S2; S2: next_state = S3; S3: begin if(X==1) next_state = S3; else next_state =S4; S4: next_state =S0; endcase

7. Traffic Light Controller – Verilog Code
//State Register (posedge clk or negedge reset) begin if(reset==0) state <= S0; else state <= next_state; end

8. Traffic Light Controller – Verilog Code
//Output Logic (state) begin case(state) S0: begin hwy = `GREEN; country = `RED; end S1: begin hwy =`YELLOW; country = `RED;end S2: begin hwy = `RED; country = `RED; end S3: begin hwy = `RED; country = `GREEN; end S4: begin hwy = `RED; country = `YELLOW; end endcase end