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שלבי ביצוע הוראת מכונה (1) FETCH = קרא הוראה מהזיכרון ע " פ הכתובת שמכיל ה -PC. (2) DECODE = פענח את הפקודה וקרא את האוגרים הנחוצים ( אחד או שניים ). (3) EXECUTE = בעזרת ה -ALU חשב את התוצאה, או כתובת רצויה. (4) MEMORY = השתמש בתוצאה לבצע במידת הצורך : או טעינה לזיכרון (Store) או קריאה מהזיכרון (Load). (5) WRITE BACK = בצע במידת הצורך טעינה לאוגר.
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במשך כל מחזור השעון קוראים בסוף השעון כותבים cycle time rising edge falling edge קווי הבקרה - מיוצרים על פי השעון, כל עליית שעון תשנה בעקבותיה את קווי הבקרה (אם נדרש)
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MIPS תיאור מפושט של מעבד החיבורים המתוארים תומכים בכל שלבי פקודות R-type ו- I-type אנו נתמוך בפקודות: add, sub, or, xor, and, slt, lw, sw, beq, j כמובן שנצטרך לדעת כיצד מוסיפים פקודות נוספות כמו למשל: bne, addi, jal, jr
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עוד שלושה שבועות
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חלקים בסיסים של המחשב הדרושים לשלב ה -fetch: Instruction Address Instruction Memory Add Sum כמובן שדרוש זיכרון פקודות, רגיסטר לשמירת הכתובת וכן adder לחשוב הכתובת הבאה
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FETCH - שלב ה Add 4 PC Read address Instruction memory 4
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A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Instruction Memory PC Adde r 4 ck 6 [31:26] 6 [5:0]= funct
![A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Instruction Memory PC Adde r 4 ck 6 [31:26] 6 [5:0]= funct](http://images.slideplayer.com/17/5366343/slides/slide_7.jpg "A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Instruction Memory PC Adde r 4 ck 6 [31:26] 6 [5:0]= funct")
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יחידת הרגיסטרים. יחידה זו דרושה לשלב ה -decode ( ולשלב ה -write back) Read register 1 Registers Read register 2 Write register Write Data Read data1 Read data2 מספרי האוגרים Data
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Arithmetic Logic operation Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 ALU Zero ALU operation ALU result Instruction ALU result ALU operation הפעולה הבסיסית שנדגים הנה פקודת R-type
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A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct
![A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct](http://images.slideplayer.com/17/5366343/slides/slide_10.jpg "A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct")
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A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct
![A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct](http://images.slideplayer.com/17/5366343/slides/slide_11.jpg "A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct")
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The internal structure of the Register File 32 Read data 2 write data Read data 1 5 5 5 Rd reg 2 (= Rt) Rd reg 1 (= Rs) RegWrite Wr reg (= Rd) 32 E קוראים משתי היציאות בוזמנית ערכים של שני רגיסטרים שונים כותבים לאחד הרגיסטרים האחרים (בעליית השעון הבאה)
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A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite
![A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite](http://images.slideplayer.com/17/5366343/slides/slide_13.jpg "A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite")
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A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU ck
![A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU ck](http://images.slideplayer.com/17/5366343/slides/slide_14.jpg "A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU ck")
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A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCPC ALU ck 4
![A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCPC ALU ck 4](http://images.slideplayer.com/17/5366343/slides/slide_15.jpg "A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCPC ALU ck 4")
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A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 6 [5:0]=funct ALU control
![A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 6 [5:0]=funct ALU control](http://images.slideplayer.com/17/5366343/slides/slide_16.jpg "A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 6 [5:0]=funct ALU control")
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Load,Store בניית פעולות Read address Data memory Write address Write data Read data Write Read כאן נדרש זיכרון ל- data ממנו נקרא ואליו נכתוב כמו כן יש לבצע sign extension של ה- imm שהוא רק 16bit
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A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out
![A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D.](http://images.slideplayer.com/17/5366343/slides/slide_18.jpg "Out.")
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A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out
![A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D.](http://images.slideplayer.com/17/5366343/slides/slide_19.jpg "Out.")
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A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out
![A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D.](http://images.slideplayer.com/17/5366343/slides/slide_20.jpg "Out.")
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A CPU capable of lw & sw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=0 16 [15:0] 5 add Sext 16->32 Data Memory D.In Address MeWrite=1
![A CPU capable of lw & sw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=0 16 [15:0] 5 add Sext 16->32 Data Memory D.In Address MeWrite=1](http://images.slideplayer.com/17/5366343/slides/slide_21.jpg "A CPU capable of lw & sw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=0 16 [15:0] 5 add Sext 16->32 Data Memory D.In Address MeWrite=1")
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A CPU capable of R-type & lw instructions (principle) 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control 5 [15:11]=Rd Address
![A CPU capable of R-type & lw instructions (principle) 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control 5 [15:11]=Rd Address](http://images.slideplayer.com/17/5366343/slides/slide_22.jpg "A CPU capable of R-type & lw instructions (principle) 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control 5 [15:11]=Rd Address")
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A CPU capable of R-type & lw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D. Out
![A CPU capable of R-type & lw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D.](http://images.slideplayer.com/17/5366343/slides/slide_23.jpg "Out.")
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A CPU capable of R-type & lw/sw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D.In D. Out MemWrite
![A CPU capable of R-type & lw/sw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D.In D.](http://images.slideplayer.com/17/5366343/slides/slide_24.jpg "Out MemWrite.")
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:Branch אלמנטים דרושים להוספת ALU Zero Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 Instruction Adder Sum Shift left2 Sigh Extend Branch Target מועבר ליחידת הבקרה כתוצאה הלוגית של ההשוואה 1632 PC+4 משלב ה- Fetch In addresses, we always shift left by two bits
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שילוב כל הפקודות Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 Zero ALU result Data Sign extend 32 Read address memory Write address Write data Read data Write Read 16 Add 4 PC M u x Read address Instruction memory ADD ALU result Shift left2 M u x M u x
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איפה ה - CPU? CPU Instruction Memory Data Memory PC
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קווי בקרה PC Instruction memory Read address Instruction 16 32 Add M u x Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 4 M u x ALU operation 3 RegWrite MemRead MemWrite PCSrc ALUSrc MemtoReg ALU result Zero ALU Data memory Address Write data Read data M u x Sign extend Add ALU result Shift left 2
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Control PC Instruction memory Read address Instruction [31–0] Instruction [20–16] Instruction [25–21] Add Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch R register 2 Sign extend Shift left 2 M u x 1 ALU result Zero Data memory Write data Rea d dat a M u x 1 Instruction [15–11] ALU control ALU Address
![Control PC Instruction memory Read address Instruction [31–0] Instruction [20–16] Instruction [25–21] Add Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch R register 2 Sign extend Shift left 2 M u x 1 ALU result Zero Data memory Write data Rea d dat a M u x 1 Instruction [15–11] ALU control ALU Address](http://images.slideplayer.com/17/5366343/slides/slide_29.jpg "Control PC Instruction memory Read address Instruction [31–0] Instruction [20–16] Instruction [25–21] Add Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch R register 2 Sign extend Shift left 2 M u x 1 ALU result Zero Data memory Write data Rea d dat a M u x 1 Instruction [15–11] ALU control ALU Address")
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ALU control ALU control output 000 AND 001OR 010add 110subtract 111set-on-less-than (sign of rs-rt -> rd) 00 = lw, sw 01 = beq, 10 = arithmetic ALUop
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פקודת ה - jump 4 bits 26 bits 2 bits 00 : כתובת קפיצה במילים : כתובת קפיצה בבתים 0110 101 … 101111011 00 101 … 1011110110110: הקפיצה הסופית : תוספת 4 ביטים אחרונים פירוש הפקודה: J 101 … 101111011 הפקודה הבאה נמצאת בכתובת 111111011…1001
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Jump Shift left 2 PC Instruction memory Read address Instruction [31–0] Data memory Read data Write data Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] Instruction [20–16] Instruction [25–21] Add ALU result Zero Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch Jump RegDst ALUSrc I sult M u x 0 10 ALU Shift left 2 2628 Address
![Jump Shift left 2 PC Instruction memory Read address Instruction [31–0] Data memory Read data Write data Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] Instruction [20–16] Instruction [25–21] Add ALU result Zero Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch Jump RegDst ALUSrc I sult M u x 0 10 ALU Shift left Address](http://images.slideplayer.com/17/5366343/slides/slide_33.jpg "Jump Shift left 2 PC Instruction memory Read address Instruction [31–0] Data memory Read data Write data Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] Instruction [20–16] Instruction [25–21] Add ALU result Zero Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch Jump RegDst ALUSrc I sult M u x 0 10 ALU Shift left Address")
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