1. 1 Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization TingTing Hwang Tsing Hua University, Hsin-Chu

2. 2 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions

3. 3 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions

4. 4 Engineering Change Order Incremental change of a design to fix bugs or to meet timing constraint To save the reiteration of design flow To reduce the cost of mask-making Spare cells (NOT, NOR, NAND) are placed evenly in layout at physical design Spare cells are then used for modification in ECO flow

5. 5 Engineering Change Order (ECO) Incremental change of a design To fix bugs To meet timing constraint To meet small change of functionality Small modification instead of redesign a circuit To save the reiteration of design flow To reduce the cost of mask-making

6. 6 Spare Cells in ECO Spare cells (NOT, NOR, NAND) are placed evenly in layout at physical design Spare cells are then used for modification in ECO flow

7. 7 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions

8. 8 Voltage Drop Power source fluctuations become serious High performance Lower supply voltage VDD/GND variations Chip speed Noise margin Adding decoupling capacitance (decap) is an effective way to reduce power noise [Sachin, TCAD 2003]

9. 9 What is Decap? Decap: decoupling capacitor

10. 10 Power noise analysis Adding decaps is an effective way to reduce power noise [Sachin, TCAD 2003]

11. 11 New ECO Design Flow A new reconfigurable (RECON) cell structure Served as spare cell and decoupling capacitor Leakage reduction Free selecting of function type Demonstration of RECON cell by an ECO algorithm for timing closure and IR drop minimization

12. 12 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions

13. 13 RECON Base Cell Two PMOS transistor with same transistor width Two NMOS transistor with same transistor width Eight CONTACTs VDD and GND implemented by layer of metal-1

14. 14 DECAP Cell VDD GND VDD Configured from RECON base cell Use Metal-1 connection Schematic of cell

15. 15 DECAP Cell Configured from RECON base cell Use Metal-1 connection Schematic of cell GND VDD GND

16. 16 Functional Cell (a) Inverter (b) 2-Input NAND (c) 2-Input NOR Configured from RECON base cell

17. 17 Comparisons Between RECON Cells and Standard Cells Setup of experiment Cell layouts created with TSMC 0.13um process SPICE net-lists extracted by RC- extractor Delay, leakage, internal power and input pin capacitance by SPICE simulation

18. 18 As Decoupling Cells Less flexibility of layout 16%-39% capacitance 9%-34% leakage

19. 19 As functional cells No need tie-high cells and tie-low cells Outperform in area and leakage Pin capacitance and delay in same level Spare cells

20. 20 As Functional Cells Area Delay Leakage PowerPin cap w/o tie-cellw/i tie-cellReconw/o tie-cellw/i tie-cellRecon INVX1 0.5010.671.020.8810.810.890.93 INVX2 0.571 1.010.9410.930.94 INVX4 0.6710.890.990.9710.930.98 INVX8 0.7911.140.98 10.891.020.98 INVX16 0.8811.330.980.9910.871.000.99 ND2X1 0.401 1.050.810.801.190.98 ND2X2 0.5010.671.050.8910.841.300.98 NR2X1 0.401 1.090.8110.791.330.98 NR2X2 0.5010.671.110.8910.861.551.04 BUFX1 0.571 0.840.9211.211.071.50 BUFX2 0.6311.00 0.9610.930.970.95 BUFX4 0.7511.000.990.9810.900.980.92 BUFX8 0.8311.330.99 10.880.990.96 Average 0.6110.821.010.9210.901.091.01

21. 21 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions

22. 22 Model of Power Supply Analysis Cycle-based time frame

23. 23 Model of Power Supply Analysis (cont.) Metal layer of VDD and GND modeled as a power-grid resistance Standard cells modeled as time-varying current source RECON DECAP cells modeled as capacitors connected between VDD and GND

24. 24 Model of Power Supply Analysis (cont.) Supply voltage variation can be derived as following Clock cycle is divided into many time slots Switching gate are derived from static timing analysis Maximum current consumption are calculated in each time slot.

25. 25 Power Supply Network VDD power stripe VSS power stripe A1 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 E1 E2 E3 E4 D1 D2

26. 26 IR Drop Analysis of Whole Chip

27. 27 Leakage Analysis of Whole Chip

28. 28 Outline Introduction Engineering Change Order (ECO) Voltage Drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental result Conclusion

29. 29 Differences Between RECON and Traditional ECO Flows RECON DECAP instead of spare cells are pre-placed RECON DECAP cells are reconfigured to RECON functional cells when RECON ECO flow is performed Unselected RECON DECAP cells are kept as decoupling capacitors

30. 30 Problem Formulation An ECO path is a path that violates the timing constraint Given a set of placed gate level net-list, ECO paths and timing constraint, perform gate sizing or buffer insertion on ECO paths Timing constraint is met IR drop is minimized

31. 31 RECON ECO Algorithm Two key observations in Synopsys ’ s timing liberty [Yen, ICCAD2007] Loading dominance Shielding effect

32. 32 RECON ECO Algorithm Input: a set of ECO paths to be optimized For each ECO path Find the critical gates in ECO paths and put in ECO_gate_list While (timing is not satisfy) Choose the gate from ECO_gate_list with most output loading Perform gate sizing or buffer insertion List_A = search_region(gate_sizing) List_B = search_region(buffer_insertion) For all configurable cell Rg in List_A or List_B If IRdrop(Rg) > threshold Remove Rg in List_A or List_B Candidate_list = List_A + List_B Compute path delay gain for all Rg in Candidate_list Select the best Rg corresponding to the best delay gain Update the ECO path delay End while

33. 33 Search Region for Gate Sizing D1 D2 D3 D4 D5 D6 Search_region(G4) = Bounding_Box(G3 U G4 U G5 U G6)

34. 34 Search Region for Buffer Insertion D1 D2 D3 D4 D5 D6 Search_region(G4) = Bounding_Box(G4 U G5 U G6)

35. 35 Outline Introduction Engineering Change Order (ECO) Voltage drop (IR-DROP) New design style Cell level Chip level New design style for ECO flow RECON ECO algorithm Experimental results Conclusions

36. 36 Experimental Setup ITC99 benchmarks Benchmarks synthesized to gate-level net-list using TSMC 0.13um process Standard cells and RECON DECAP cells placed by SOCEncounter 20% area used to place RECON DECAP cells

37. 37 Experimental Flow

38. 38 Statistics of Benchmarking Circuits Timing constraint is set to 90% of critical path delay in the original circuit

39. 39 Leakage Comparisons Before ECO

40. 40 Performance Comparisons Before ECO Trad: traditional spare cells RECON: RECON decap cells

41. 41 Performance Comparisons After ECO Trad: traditional spare cells RECON: RECON decap cells

42. 42 Number of Unsolved Paths After ECO Trad: traditional spare cells RECON: RECON decap cell

43. 43 Conclusions A new cell structure Decoupling capacitor cell ECO spare cell A reconfigurable ECO flow 20% IR drop reduction 44% leakage reduction

44. 44