1. 9/27/05ELEC 5970-001/6970-001 Lecture 91 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power: Glitch-Free ASICs Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 9/27/05ELEC 5970-001/6970-001 Lecture 92 Motivation Application Specific Integrated Circuit (ASIC) chips employ standard cell design style. Dynamic power consumed by glitches in a CMOS circuit, though significant, can be reduced or eliminated by design. Existing glitch reduction techniques demand customized gate design, not suitable for a standard cell ASIC.

3. 9/27/05ELEC 5970-001/6970-001 Lecture 93 Power Dissipation in CMOS Logic (0.25µ) %75%5%20 P total (0→1) = C L V DD 2 + t sc V DD I peak + V DD I leakage CLCL

4. 9/27/05ELEC 5970-001/6970-001 Lecture 94 Prior Work: Hazard Filtering Glitch is suppressed when the inertial delay of gate exceeds the differential input delay. 1 or 3 2 Filtering Effect of a gate Reference: V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997. or 2 2

5. 9/27/05ELEC 5970-001/6970-001 Lecture 95 Prior Work: A Reduced Constraint Set LP Model for Glitch Removal Satisfy glitch suppression condition at all gates: Differential path delay at gate input < inertial delay Use a linear program (LP) to find delays –Path enumeration avoided –Reduced (linear) size of LP allows scalability Design gates with specified delays 40-60% dynamic power savings in custom design Procedure is not suitable for pre-designed cell libraries Reference: T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” VLSI Design 2003.

6. 9/27/05ELEC 5970-001/6970-001 Lecture 96 Prior Work: ASIC J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ’01 –Transistor sizing results in 20 - 25% savings in power –Power optimized by minimizing parasitic capacitances –No glitch reduction attempted Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ’01 –Mixed Integer Linear Program (MILP) to select from different realizations of cells such that power consumption is minimized without violating delay constraints –Sum of dynamic and leakage power is minimized –Library contains cells of varying sizes, supply voltages, and threshold voltages –Achieved 79% power saving on an average –No glitch reduction attempted.

7. 9/27/05ELEC 5970-001/6970-001 Lecture 97 A Glitch-Free Design Balance differential delays at cell inputs: –Use Resistive Feedthrough cell delay elements Automate the design –Customized delay cell generation –Insertion into the circuit

8. 9/27/05ELEC 5970-001/6970-001 Lecture 98 Delay Elements Inverter pair: delay controlled by W/L of transistors. Diffusion capacitor: n-diffusion, SiO2, polysilicon. Polysilicon resistor: R □ L/W –Sheet resistance (0.25μ CMOS process) R □ = 3.6Ω/square, with silicide R □ = 173.6Ω/square, with silicide masked Transmission gate

9. 9/27/05ELEC 5970-001/6970-001 Lecture 99 Evaluation of Delay Elements

10. 9/27/05ELEC 5970-001/6970-001 Lecture 910 Comparison of Delay Elements Delay element Average delay (ns) Delay/ Power ns/μW Delay/ Area ns/grids I0.280.220.03 II0.310.230.05 III0.440.330.11 IV0.350.220.16 II. n diffusion capacitor(2.7fF) III. Polysilicon resistor (15.4kΩ) IV. Transmission gate I. Inverter pair Resistor shows –Maximum delay –Minimum power and area per unit delay –Hence, best delay element Resistive feed through cell –A fictitious buffer at logic level

11. 9/27/05ELEC 5970-001/6970-001 Lecture 911 Resistive Feedthrough Cell A parameterized cell Physical design is simple – easily automated No routing layers(M2 to M5) used – not an obstruction to the router R □ *(length of poly) Width of poly R = S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004.

12. 9/27/05ELEC 5970-001/6970-001 Lecture 912 RC Delay Model C L varies during transition ( model not perfectly linear) Spectre simulation data stored as a 3D lookup table Average of signal rise and fall delays Linear interpolation used T PLH + T PHL 2 T P = Vin R CLCL Vout CLCL R TPTP

13. 9/27/05ELEC 5970-001/6970-001 Lecture 913 Design Optimization Flow Design Entry Tech. Mapping Layout Remove Glitches Find delays from LP Find resistor values from lookup table Generate feed through cells and modify netlist

14. 9/27/05ELEC 5970-001/6970-001 Lecture 914 Results Circuit New Standard Cell Based Design Power saved (%) in custom design Raja et al. Area overhead (%) Power saved (%) 4 bit ALU29.523.7N/A c432114.050.035.0 C49986.032.029.0 C88098.043.044.0 C135522.068.356.0 C267014.030.031.0 S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004.

15. 9/27/05ELEC 5970-001/6970-001 Lecture 915 Glitch Elimination on net86 in 4-bit ALU Source: Post layout simulation in SPECTRE

16. 9/27/05ELEC 5970-001/6970-001 Lecture 916 Layouts of c880 Original layout of c880 Optimized layout of c880 Power saving = 43% Area increase= 98%

17. 9/27/05ELEC 5970-001/6970-001 Lecture 917 Reference S. Uppalapati, M. L. Bushnell and V. D. Agrawal, “Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells,” Proc. 9 th VLSI Design and Test Symp., Aug. 11-13, 2005, pp. 41-48.

18. 9/27/05ELEC 5970-001/6970-001 Lecture 918 Conclusion Successfully devised a glitch removal method for the standard cell based design style Does not require redesign of the library cells Does not increase the critical path delay Modified design flow maintains the benefits of ASIC On an average Dynamic power saving: 41% Area overhead: 60% Possible ways to reduce area overhead Cell replacements from existing library On-the-fly-cell design Adjust routing delays for glitch suppression

19. 9/27/05ELEC 5970-001/6970-001 Lecture 919 Custom Design Model gates with input and output delays. Gate Output delay = d Input 1 Input 2 d1 d2 Delay = d + d2 Delay = d + d1 0 ≤ d1, d2 ≤ ub

20. 9/27/05ELEC 5970-001/6970-001 Lecture 920 Determination of Delays Determine the realizable upper bound (ub) on gate input differential delay by simulation of gates and delay elements. Determine input and output delays for all gates for glitch suppression. Implement gates with required delays. References: 1.T. Raja, V. D. Agrawal and M. L. Bushnell, “Design of Variable Input Delay Logic for Low Dynamic Power Circuits,” Proc. PATMOS, Sep 2005. 2.T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay Logic and Its Application to Low Power Design,” Proc. 18 th Int’l. Conference on VLSI Design, Jan 2005, pp. 596-603. 3.T. Raja, V. D. Agrawal and M. L. Bushnell, “CMOS Design of Circuits for Minimum Dynamic Power and Highest Speed,” Proc. 17 th Int’l. Conference on VLSI Design, Jan 2004, pp. 1035-1040.

21. 9/27/05ELEC 5970-001/6970-001 Lecture 921 Implementation of Delays Gate delay = d+d1 VDD d1 < d2 Delay = d2-d1

22. 9/27/05ELEC 5970-001/6970-001 Lecture 922 Design of c7552 Circuit Un-optimized Gate Count= 3827 Transistor Count ≈ 40,000 Critical Delay = 2.15 ns Area= 710 x 710 μm 2 Optimized Gate Count= 3828 Transistor Count ≈ 45,000 Critical Delay = 2.15 ns Area= 760 x 760 μm 2 (1.14)

23. 9/27/05ELEC 5970-001/6970-001 Lecture 923 Instantaneous Power by Spice Power Saving: Peak 68%, Average 58%

24. 9/27/05ELEC 5970-001/6970-001 Lecture 924 Energy Measured by Spice Power Saving: Average 58%