1. مرتضي صاحب الزماني  The registers are master-slave flip-flops (a.k.a. edge-triggered) –At the beginning of each cycle, propagate values from primary inputs and from register outputs into combinational blocks (CBs). –Compute the stable outputs of CBs, and store them in register inputs (they’ll move to outputs in the next cycle). CB RTL model Cycle-based Simulation

2. مرتضي صاحب الزماني  It divorces functional behavior from timing: –Functionality and timing can be verified separately –Dealing with each of the above, we have fewer details to worry about (divide and conquer!) –Within each cycle, we can assume that all signal changes occur in zero- delay Only evaluate on the clock edge First: evaluate all combinational logic Next: latch values into state registers Repeat on next clock edge 1 0 Cycle 1Cycle 2Cycle 3 t Steady state Assume ‘zero-delay’ (don’t care about the transient delays) Zero-delay cycle-based simulation

3. مرتضي صاحب الزماني  Within each Combinational Block, gates can be levelized (sorted in topological order) for evaluation.  Going by level number, every gate will be evaluated after its inputs have been computed.  So: we order the gates by the flow of data, and we don’t care about the real delays - > assume “0 delay”.  Combinational Feedbacks? A levelized CB Levelizing the gates

4. مرتضي صاحب الزماني Event vs. Cycle-based Simulation

5. مرتضي صاحب الزماني Cycle-based versus Event- driven Cycle-based:Cycle-based: –Only boundary nodes –No delay information Event-driven:Event-driven: –Each internal node –Need scheduling and functions may be evaluated multiple times Cycle-based does not detect glitches and setup/hold time violations, while event-driven does Treats everything in the design description as either clocked element or zero- delay combinational logicTreats everything in the design description as either clocked element or zero- delay combinational logic

6. مرتضي صاحب الزماني Simulation: Perfomance vs Abstraction.001x SPICE Event-driven Simulator Cycle-based Simulator 1x10x Performance and Capacity Abstraction

7. مرتضي صاحب الزماني Why is it faster? FF Z a b c d Node a has 5 transitions and b has 3 transitions. Event-driven simulator reevaluates when inputs change  Gate A simulates 5 times, Gate B: 9 times, Gate C: 6 times Total 20 times. But simulates only these 3 gates. A B C Cycle-based simulator simulates the entire circuit only once (at the end of current cycle)  All Gates in the circuit are simulated regardless whether their inputs have been changed. Conclusion: Event-driven is faster if few transitions (typically less than 5% active nodes). In practice, experiments confirm that a cycle-based simulator is almost always 5-10 times faster (and uses less memory)

8. مرتضي صاحب الزماني Special Considerations Asynchronous circuits cannot be simulated by cycle- based simulators.

9. مرتضي صاحب الزماني Special Considerations False Loops should be eliminated –A loop that consists of combinational gates but signals cannot propagate around the loop in any one cycle. –Event-driven has no problem. 1 1 0 0

10. مرتضي صاحب الزماني Special Considerations Clock gating: –In cycle-based: FF2 is only evaluated on transitions of clk2 If FF1 toggles between two edges of clk2, FF2 is not evaluated  Error. FF2 FF1 clk2 clk1

11. مرتضي صاحب الزماني Hardware Simulators 1.Uses FPGA to mimic the design Design is synthesized i.t.o. gate netlist Then FPGAs are mapped to netlist and are programmed. 2.Special Processor directly simulates the circuit: Has bit operators, AND, OR, MUX and HDL operators  Circuit is compiled to the processor’s machine code and simulated.