1. 1 Richard B. Brown CANDE Workshop September 11-13, 2003 Taos, New Mexico Richard B. Brown Michael S. McCorquodale brown, mccorq@umich.edu Analog Mixed Signal Low-Power Microcontrollers

2. 2 Richard B. Brown Fundamental Changes in Microprocessor Market 1975 to 2000 –Performance drove demand Desktop Processors –US market is saturating –Performance is now adequate Less motivation to upgrade –Performance is limited by power dissipation –Cost is comparatively more important Servers and Video Processors –Performance is limited by power dissipation Portable Computers –Battery operation calls for lower power Where are the new markets? –Communications, Networking, and Microsystems

3. 3 Richard B. Brown Generalized Microsystem MEMSAnalogMixed-SignalDigital/VLSI Antenna Microprocessor Wireless Interface Clock Sensor/Actuator Interface Sensor Actuator Baseband Modem RFIC/RFMEMS FE Tools AHDL Custom IC Tools VHDL Synthesis Tools AHDL Custom RFIC Tools DAC ADC MS-HDL Custom IC Tools Technologies Components Design Tools Electrical, Magnetic, Mechanical, Chemical, Optical, Biological

4. 4 Richard B. Brown MS-8 Mixed-Signal Microcontroller TWM Timers MFT Timers USART Parallel I/O Prog. Mem. Data Mem. CLK Manager MAC Processor Core Control Analog Interface PGA LPF Bandgap Reference 12-bit  ADC 16-bit Slope ADC Temp. Sensor Ampero- metric Interface Capacitive Interface Voltage K. Kraver, et al., Hilton Head Sensors and Actuators Conf., June 2000.

5. 5 Richard B. Brown Programmable Gain Amplifier (PGA) Large input impedance, small output impedance Differential to single-ended conversion DC Level shifting Gain controlled by R 1 : 1, 11, 21, 31, 41, 51, 61 V/ V R2R2 R3R3 R3R3 R3R3 R3R3 R1R1 R2R2 V inp V inm V out V ref

6. 6 Richard B. Brown Ramp Generator Potentiostat Reference Counter Working Amperometric Cell RfRf R2R2 R1R1 V ref to mux 1 2 3 4

7. 7 Richard B. Brown Capacitive Sensor Readout Programmable internal reference capacitor Four input sensor mux V ref V(C s ) reset C ref CsCs CfCf reset  VAVA 

8. 8 Richard B. Brown Bottom-Up Design Methodology Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool) Verification: DRC, LVS (Top Routing Only), Parasitic ExtractionandBackannotation (IC Tool) Digital SpecificationAnalog SpecificationMechanical Specification Custom Analog Design (SPICE) Custom Mechanical Design (FE) Synthesis/APR/Timing (Synthesizer) Analog Physical Design (IC Tool) Digital Library Tapeout Process Library Digital Design (HDL) Digital Domain Analog Domain Mechanical Domain Analog MacroMechanical MacroDigital Macro System Specification and Design Partition Macro Automatic Place and Route (APR and IC Tool)

9. 9 Richard B. Brown Bottom-Up Design Methodology Problems Time-consuming design iteration Cross-domain verification at top level only Time-consuming system level simulation, if it is possible at all No opportunity for architectural studies

10. 10 Richard B. Brown Mixed-Signal Microcontrollers Die size: –3.8 x 4.1 mm 2 (total) –3.0 x 2.6 mm 2 (core) 0.35  m CMOS 303K transistors 103 I/O, 12 power MS-8

11. 11 Richard B. Brown Solid-State Sensor Advantages 3.5 x 4.8 mm Sensicore Sensor Arrays Convenience Accuracy Speed Shelf Life Cost Size Potentiometric Conductometric Temperature Amperometric ORP

12. 12 Richard B. Brown Salinity Water Parameters TestSelective Ligand / Exchanger Range – (Molar units) PotassiumK+K+ PU- Valinomycin10 -5 --10 -1 SodiumNa + PU- Calixarene10 -4 –10 -1 HydroniumpHTri-n-dodecylamine5-9 Calcium Ca ++ PU- ETH 100110 -5 –10 -2 ChlorideCl - Quaternary Ammonium Poly10 -4 –10 -1 AlkalinityHCO3 - Differential Membrane pH3x10 -3 –10 -1 OxygenpO 2 Silicone/Nafion®0-300 mmHg AmmoniaNH 3 Silicone- diff. pH or Ammonium ion10 -5 --10 -1 ChlorineCl 2 Cellulose- HOCl reduction1-10 ppm Oxidation - Reduction ORPPotential0-1000 mV TemperatureRTD5--50 o C ConductivityTi/Pt 0--2000  S/cm Potable Water Testing

13. 13 Richard B. Brown Sensors Amperometric –Three terminal sensors –Voltage applied across reference and working electrodes –Current measured at the auxiliary node –Measured using cyclic voltammetry Analyte peaks at varying voltages Current depends on concentration Dopamine Serontonin Cyclic Voltamagrams

14. 14 Richard B. Brown Neurological Sensor Array

15. 15 Richard B. Brown Lead Detection by Pulse Voltammetry E, V -2.00E-07 -1.80E-07 -1.60E-07 -1.40E-07 -1.20E-07 -1.00E-07 -8.00E-08 -6.00E-08 -4.00E-08 -2.00E-08 0.00E+00 -0.6-0.4-0.200.20.40.60.81 E, V i, A 0 ppb 25 ppb 98 ppb 195 ppb 390 ppb

16. 16 Richard B. Brown Arsenic Detection by Pulse Voltammetry -1.10E-06 -9.00E-07 -7.00E-07 -5.00E-07 -3.00E-07 -1.00E-07 00.10.20.30.40.50.60.7 Voltage, V Current, A 0 ppb 5 ppb 10 ppb 15 ppb 20 ppb

17. 17 Richard B. Brown Test Setup GND 3 V +12 V -12 V 2.80 V 0.20 V 3 V CLK LabView MS-8 Test Board program data RS-232 buffer reset

18. 18 Richard B. Brown Potentiometric Sensor Demo

19. 19 Richard B. Brown Potentiometric Sensor Results Calibration Curve for Potassium Time Response: each step represents a decade jump in potassium concentration V = 0.0525Log(C) + 1.8211 R 2 = 0.9998 V = 0.0525Log(C) + 1.8211 R 2 = 0.9998 PGA gain = 1 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 1 Molarity Potassium

20. 20 Richard B. Brown Wireless Integrated MicroSystems (WIMS) ERC Environmental Sensors Biomedical Implants Cochlear Implant Medtronics Deep Brain Implants

21. 21 Richard B. Brown Micropower Circuit Goals Acceptable Performance –ADC Speed and Accuracy –Digital Processing Speed Very Low Power –Implantable –Single Battery Cell Compatibility –Sensor Interfaces –Wireless/Network Interfaces –Software - C Flexibility – Efficiency Trade-off –Circuit Reusability CC ADC I/O Sensor Interface Temp Sensor Memory Power Management RF Base- band

22. 22 Richard B. Brown WIMS Architecture 16-bit Instruction Encoding –Most Instructions are two bytes –Power-Efficient ISA 16-bit Datapath –12-bit sensor data Loop Cache Static Logic Clocks –Gated –Frequency Control –Idle/Wake-Up Minimize Dynamic Power –Switching Activity – Memory Accesses Advanced Process – Low Voltage – Low Capacitance C Code Power Efficiency

23. 23 Richard B. Brown Design Framework Requirements System level simulation support (HDL) Cross-domain verification –Analog and digital electronics, and MEMS Finite element simulation Active device and HDL simulation Parasitic extraction Co-simulation of primitives and HDL Timing verification HDL synthesis Automatic place and route

24. 24 Richard B. Brown Design Tools Employed Cadence AMS System modeling, primitive/HDL co-simulation, and MEMS modeling Cadence Spectre Analog device level simulation Coventorware Finite element analysis Artisan Logic and Memory Libraries Synopsys Digital synthesis Cadence Silicon Ensemble Automatic place and route Mentor Graphics Calibre DRC, ERC, and LVS

25. 25 Richard B. Brown Tapeout Top-Down Design Methodology Cross-Domain Verification (Verilogwith updatedVerilog-A from achieved performance and/orVerilogandVerilog-A with Primitives) Analog Model (Verilog-A) Mechanical Model (Verilog-A) Abstract System Model (Verilog-AMS:VerilogandVerilog-A) Digital Library Process Library Digital Domain Analog Domain Mechanical Domain Cross-Domain Verification (Verilogwith updatedVerilog-A fromparasiticsand/orVerilogandVerilog-A with Primitives) Cross-Domain Verification (Verilogwith updatedVerilog-A with interconnectparasitics) Analog Macro Parasitic Extraction (IC Tool) Extraction, Timing (Timing Tool) Digital MacroMechanical Macro Parasitic Extraction (IC Tool) Custom Analog Design (SPICE) Mechanical Design (Finite Element) Macro Place and Route, Layout Verification: DRC, LVS (APR and IC Tool) Layout Parasitic Extraction (LPE) andBackannotation (IC Tool) Synthesis/APR/Timing (Synthesis Tool) Physical Design/Verif. (IC Tool) Physical Design/Verif. (IC Tool) Digital Model (Verilog) Behavioral Verification (Verilog) M. McCorquodale, DATE, March 2003.

26. 26 Richard B. Brown 0.18  m TSMC CMOS 0.9 – 1.8V Power Supply Components –Input Buffers –Programmable Gain Amplifier –Second-Order  Converter –Third-Order Comb Filter Features –Subthreshold Operation –Switched-Capacitor Circuits –Clock Doubling –Switched OpAmps –Body Biasing Low-Voltage Analog to Digital Converter

27. 27 Richard B. Brown WIMS Microcontroller Fabricated in TSMC 0.18  m CMOS 8KB RAM 8KB RAM 8KB RAM 8KB RAM CORECORE IOIO CLK AFE WIMS Microcontroller TSMC 0.18 micron mixed-mode 16-bit 3-stage pipeline core Analog front end (AFE) MEMS-based clock generator 32 KB on-chip SRAM Timer and serial interfaces 1.5 million transistors 10.24mm2 Estimated Power 24 mW @ 100 MHz R. Senger, et al., DAC, June 2003.

28. 28 Richard B. Brown Gaps and Solutions Gaps in the Tool Suite MEMS and analog simulation results not automatically extracted to behavioral model Lack of physical verification for MEMS components No synthesis capabilities for MEMS from topological or behavioral models Inability to port designs between process technologies Solutions & Future Direction Custom and manual extraction: Requires design automation Custom mod. of DRC/LVS decks: Requires support No current solution: Requires design automation

29. 29 Richard B. Brown Synthesis of MEMS Blocks Specific Devices Supported –Free-Free Beam Resonators –Clamped-Clamped Beam Resonators –Varactors, several configurations User Interface –Enter Process Characteristics –Enter Operational Specifications Proprietary Algorithms Generate Dimensions –Calls to MatLab and/or Mathematica Output –Plots –Electrical Model –Physical Design Parameters User Input for further Customization Generation of Physical Layout Output of Physical and Electrical Models

30. 30 Richard B. Brown IP Repository M. McCorquodale, et al., IFIP VLSI SoC 2003, Darmstadt, Dec. 2003.

31. 31 Richard B. Brown Low-Power Microprocessor Status Top-Down Design Flow Low Dynamic and Static Power Dissipation –Reduced Switching –Scaled Processes, SOI –Subthreshold and Gate Leakage Processor Architecture –Efficient Instruction Set –Minimized Memory Accesses –Matched to Tasks –Dynamic Clock Scaling Power-Efficient Physical Design –Transistor Sizing –Datapaths Low-Power Analog –Subthreshold Operation –Bag of Tricks Power-Aware Software –C Compiler –Loop Cache

32. 32 Richard B. Brown Conclusions Microsystem design methodologies are in their infancy Current methodologies reflect disparate nature of the technologies Top-down methodology leverages advances in mixed-signal design automation –Far superior verification Gaps in tool suites must be addressed for microsystems design –MEMS synthesis –Better analog synthesis –Automatic model extraction to AMS

33. 33 Richard B. Brown Acknowledgements Ph.D. Students –Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, Matthew Guthaus CAD Vendors –Cadence, Synopsys, Coventor, Mentor, Artisan National Semiconductor MOSIS IBM