1. 3.3 CMOS Logic 1. CMOS Logic Levels NextReturn Logic levels for typical CMOS Logic circuits. Logic 1 (HIGH) Logic 0 (LOW) Undefined Logic level 5.0V 3.5V 1.5V 0.0V

2. 3.3 CMOS Logic 2. MOS Transistors  A MOS transistor can be modeled as a 3- terminal device that acts like a voltage controlled resistance. V IN  In digital logic applications, a MOS transistor is operated so its resistance is always either very high (and the transistor is “ off ” ) or very low (and the transistor is “ on ” ). NextBackReturn

3. 3.3 CMOS Logic  n-channel MOS (NMOS) NextBackReturn Increase V gs →decrease R ds Normally, V gs ≥ 0 V gs =0 → R ds  10 6 (  ) → I  10 -6 (A)  0 gate drain source V gs + - drain gate source V gs + - V gs  V gs(th) → R ds  10 (  ) << R L →V Rds  0

4. 3.3 CMOS Logic  p-channel MOS (PMOS) NextBackReturn Decrease V gs →decrease R ds Normally, V gs  0 V gs =0 → R ds ≥ 10 6 (  ) V gs  V gs(th) → R ds  10 (  ) gate drain source V gs + - drain gate source V gs + - Switch Model

5. 3.3 CMOS Logic 3. Basic CMOS Inverter Circuit NextBackReturn V IN Q1Q1 Q2Q2 V OUT 0.0(L) off on 5.0(H) V DD =+5.0V V IN V OUT Q 2 (PMOS) Q 1 (NMOS) V DD =+5.0V V IN =L V OUT =H V DD =+5.0V V IN =H V OUT =L 5.0(H) on off 0.0(L)

6. 3.3 CMOS Logic  CMOS inverter logical operation NextBackReturn A V DD =+5.0V Z Q 2 (PMOS) Q 1 (NMOS) On when V in is low. On when V in is high. AZ 0101 1010 Truth table for CMOS inverter

7. A V DD Z B Q1Q1 Q2Q2 Q3Q3 Q4Q4 3.3 CMOS Logic NextBackReturn 4. CMOS NAND Gates ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 Z LLHHLLHH LHLHLHLH off on off on off on off on off HHHLHHHL ABZ 00110011 01010101 11101110 A=L V DD B=L Z=H V DD A=L B=H Z=H V DD A=H B=L Z=H V DD A=H B=H Z=L A B Z

8. 3.3 CMOS Logic NextBackReturn 5. CMOS NOR Gates ABQ1Q1 Q2Q2 Q3Q3 Q4Q4 Z LLHHLLHH LHLHLHLH off on off on off on off on off HLLLHLLL ABZ 00110011 01010101 10001000 B A V DD Z Q4Q4 Q2Q2 Q1Q1 Q3Q3 A B Z

9. 3.3 CMOS Logic NextBackReturn 6. Fan-In In principle, you could design a CMOS NAND or NOR gate with a large number of inputs. A 3-input CMOS NAND gate is showed in the figure. A V DD Z B Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q6Q6 C Q5Q5 Why couldn't a CMOS gate has large number of inputs?

10. 3.3 CMOS Logic NextBackReturn Fan-In The number of inputs that a gate can have in a particular logic family is called the logic family ’ s fan-in. The fan-in of CMOS gates is typically 4 for NOR gates and 6 for NAND gates. Why is the fan-in of CMOS gates for NOR gates less than the ones for NAND gates? A n -channel transistor has low “ on ” resistance than a p -channel transistor. As a result, a k -input NAND gate is generally faster than a k -input NOR gate.

11. 3.3 CMOS Logic NextBackReturn Fan-In As the number of inputs is increased, designers of CMOS gate circuits may compensate by increasing the size of the series transistors to reduce their resistance and the corresponding switching delay. I2 I3 I4 I1 OUT I6 I7 I8 I5 I2 I3 I4 I1 I6 I7 I8 I5 OUT

12. 3.3 CMOS Logic 7. Noninverting Gates (P93)  AND Gate  OR Gate 8. CMOS AND-OR-INVERT Gate (P94) 9.CMOS OR-AND-INVERT Gate (P95) NextBackReturn

13. 3.3 CMOS Logic 10. CMOS Steady-State Electrical Behavior NextBackReturn 1.5 3.5 5.0 1.53.55.0 V out V in HIGH undefined LOW undefined HIGH Typical input-output transfer characteristic of a CMOS inverter

14.  V OLmax : The maximum output voltage in the LOW state. V OLmax =ground+0.1V 3.3 CMOS Logic  Logic Levels and Noise Margins NextBackReturn 0.7Vcc 0.3Vcc 0 Vcc ABNORMAL HIGH LOW V OHmin V IHmin V ILmax V OLmax High-state DC noise margin Low-state DC noise margin  V OHmin : The minimum output voltage in the HIGH state. V OHmin =V CC –0.1V

15.  DC noise margin: is a measure of how much noise it takes to corrupt a worst-case output voltage into a value that may not be recognized properly by an input. HIGH-state DC noise margin: V OHmin -V IHmin LOW-state DC noise margin: V ILmax -V OLmax 3.3 CMOS Logic  V IHmin : The minimum input voltage guaranteed to be recognized as a HIGH. V IHmin =0.7V CC NextBackReturn  V ILmax : The maximum input voltage guaranteed to be recognized as a LOW. V ILmax =0.3V CC

16. Regardless of the voltage applied to the input of a CMOS device, only the leakage current of the transistors connected to input. This is in sharp contrast to bipolar logic circuits like TTL oe ECL, whose inputs consume significant current (and power) in one or both states. 3.3 CMOS Logic  I IH : The maximum current that flows into the input in the HIGH state. NextBackReturn  I IL : The maximum current that flows into the input in the LOW state.

17. 3.3 CMOS Logic  Circuit Behavior with Resistive Loads NextBackReturn  Resistive Loads : (P102).  I OHmax : The maximum current that the output can sink in the HIGH state while still maintaining an output voltage no less than V OHmin.  I OLmax : The maximum current that the output can sink in the LOW state while still maintaining an output voltage no greater than V OLmax.

18.  Overall Fanout : is the minimum of the HIGH-state and LOW-state fanouts. 3.3 CMOS Logic  Fanout : The fanout of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications. NextBackReturn  DC Fanout : the output in a constant state (HIGH or LOW).

19. 3.3 CMOS Logic NextBackReturn  Transition Time : The amount of time that output of a logic circuit takes to change from one state to another. 11. CMOS Dynamic Electrical Behavior trtr tftf trtr tftf V IHmin V ILmax (a) ideal case (b) approximation (C) actual case

20. 3.3 CMOS Logic  Rise time( t r ) : the amount of time an output voltage takes to pass through the “undefined” region from LOW to HIGH. NextBackReturn  Fall time( t f ) : the amount of time an output voltage takes to pass through the “undefined” region from HIGH to LOW. The rise and fall times of a CMOS output depend mainly on two factors, the “on” transistor resistance and the load capacitance.

21. 3.3 CMOS Logic  Propagation Delay : the amount of time that it takes for a change in the input signal to produce a change in the output signal. NextBackReturn t pHL t pL H Propagation delays for a CMOS inverter  t pH L : The time between an input change and the corresponding output change when the output is changing from HIGH to LOW.  t p L H : The time between an input change and the corresponding output change when the output is changing from LOW to HIGH.

22.  Static power dissipation: The power consumption of a CMOS circuit whose output is not changing. 3.3 CMOS Logic NextBackReturn t pHL t pL H 50% V IH 50% V OH Propagation delays for a CMOS inverter measured at midpoints of transitions  Power Consumption

23. P T : The circuit’s internal power dissipation due to output transitions. C PD : The power- dissipation capacitance. f : The transition frequency of the output signal.  Dynamic power dissipation: The power consumption of a CMOS circuit whose output is changing. It’s significant. 3.3 CMOS Logic NextBackReturn Most CMOS circuits have very low quiescent power dissipation. This is what makes them so attractive for laptop computers and other low- power application.

24. 3.3 CMOS Logic NextBackReturn P L : the total amount of power dissipated by charging and discharging C L. C L : capacitive load on the output. The total dynamic power dissipation P D of a CMOS circuit is the sum of P T and P L. Based on this formula, dynamic power dissipation is often called CV 2 f power.

25. (2) A slightly overloaded circuit will fail. Loading an output beyond its rated fanout will make the output voltage( V OL ) increase beyond V OLmax in the LOW state, and the output voltage( V OH ) fall bellow V OHmin in the HIGH state, and propagation delay to the output increase beyond specification, and out rise and fall times increase beyond specification, and the operating temperature of the device increase. 3.3 CMOS Logic NextBackReturn Notice (1) The output voltage will move away from the power-supply rail with nonideal inputs.

26. An unused AND or NAND input can be tied to logic 1. 3.3 CMOS Logic (3) An unused inputs can be tied to another. NextBackReturn A B F C A B F C +5V 1k  pull-up resistor pull-down resistor An unused OR or NOR input can be tied to logic 0. A B F C 1k 

27. 3.3 CMOS Logic A pull-up or pull-down resistor is usually used. The resistor value is typically in the range 1-10k . Such a single resistor can serve multiple unused inputs. It is also possible to tie unused inputs directly to the appropriate power-supply rail. NextBackReturn Unused CMOS inputs should never be left unconnected (or floating). Why?

28. 3.3 CMOS Logic (4) Systems that use CMOS circuits require decoupling capacitors between V CC and ground. NextBackReturn (5) ESD(Electro-Static Discharge) may damage the insulation between an input transistor ’ s gate and source and drain, causing a short-circuit between the device ’ s input and output.

29. 3.3 CMOS Logic NextBackReturn How can you create a 2-input multiplexer using transmission gates? (P123) 12. Transmission Gates EN_L EN A B EN_L=0 EN=1 A B EN_L=1 EN=0 A B

30. 3.3 CMOS Logic NextBackReturn 13. Schmitt-Trigger Inputs Voltage of hysteresis =V T+ -V T- V OUT V IN V T- V T+ 2.12.9 5.0

31. EN A B C D Q1 Q2 OUT L L H H L off off Hi-Z L H H H L off off Hi-Z H L L H H on off L H H L L L off on H 3.3 CMOS Logic NextBackReturn 14. Three-State Outputs V CC OUT C D A B EN A OUT V CC OUT C D A EN V CC OUT C D A EN V CC OUT C D A EN

32. 3.3 CMOS Logic NextBackReturn 15. Open-Drain Outputs B V CC Z Q2Q2 Q1Q1 A A B Q1 Q2 Z L L off off open L H off on open H L on off open H H on on L A B Z RPRP A B Z VPVP RLRL Pull-up resistor

33. 3.3 CMOS Logic NextBackReturn  Pull-up resistor calculation A B Z=V OHmin VPVP RPRP I LH I OHmin RLRL Open-drain gates can be useful in driving light-emitting diodes (LEDs) and other devices; performing wired logic; and driving multisource buses. A B Z=V OHmin VPVP RPRP I LL I OLmax RLRL

34. 3.3 CMOS Logic NextBackReturn 16. CMOS Logic Families The first commercially successful CMOS family was 4000-series CMOS. 74 FAM nn prefix Alphabetic family mnemonic Numeric function designator

35. 3.3 CMOS Logic  HC: High-speed CMOS  HCT: High-speed CMOS, TTL compatible  VHC: Very High-speed CMOS  VHCT: Very High-speed CMOS, TTL compatible Electrical characteristics of the HC, HCT, VHC, and VHCT are different. They are summarized on page 137-144 in the text-book. BackReturn