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Students: Shalev Dabran Eran Papir Supervisor: Mony Orbach In association with: Spring 2005 High Speed Digital Systems Lab
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Project Goals Developing a 16bit CRC-GENRATOR for the Rocket I/O experiment using to the Virtex II-pro PPC To PC Packet Generation Patterns PLB Test Status Storage Traffic Generator Traffic Analyzer Rocket I/O Transceiver BRAM 1 BRAM 2 CRC Generator CRC Analyzer
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Properties Data rate – up to 2.5 Gbits /sec. Data width - 32 bits / cycle. Data length is unlimited.
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What is CRC? When we transmit message we want to be sure that the message that was received in the destination is the same one that we sent. We add to the transmitted message an overhead data for checking it on the received side. The overhead data called CRC - Cyclic Redundancy Checking. CRC are used for error detection in communication systems.
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Requirements On the transmitted side: We get double word stream of data with start_of_data packet and end_of_data packet. We add a CRC word to the end_of_data packet. On the received side: Compare the calculated CRC & the received CRC. Output an error signal if error detected
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8 bit CRC
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8 bit CRC solution to 32 bit data DATA D31 D30 D0 … ………………………… D31 CRC=D0 + + D31
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Transmitter Integration Rocket I/O Transceiver CRC Generator Traffic Generator DATA Control DATA+ CRC Control Data
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Receiver Integration Rocket I/O Transceiver CRC Analyzer Traffic Analyzer DATA Control DATA+ CRC Control Data
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Tests CRC test – by known vector. Changing Polynomial. Integrating in the complete system. Bypass test. Error injection.
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Changing Polynomials The matrix is written in the internal ram We can change it by write a new values to the ram with out the need of VHDL code changes.
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VHDL Implementation
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Test Bench
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Transmitter Side
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Handling the two CRC’s We use a XOR function to compare the two CRC’s (received and calculated). If the data that was sent and the data that was received are identical the CRC’s are the same and there will be no error. –XOR : ‘1’ ’1’ and ‘0’ ’0’ = ‘0’ ‘0’ ’1’ and ‘1’ ’0’ = ‘1’
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Receiver Side
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Error Inject
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Our CRC Vs. Web CRC Our is flexible, the web’s constant Our pipeline is better (one gate between latches). Our area is much Bigger. We use around 5000 latches the web can be uses around 200.(Transmiter and Receiver) Main different is the latches, area & timing
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Summary Our part in this project was to add 16 bit changeable parallel CRC to both the Transmitter part and the receiver part. We check the differences between a serial and a parallel implementation and decided to go with a specific implementation that we can use to simply modify the polynomial that is being used. CRC block features: –Can be bypassed using a bypass signal. –Can be intentionally inserted error using the error inject signal. –Can used different polynomials by changing the chip internal memory without changing the VHDL code. After the implementation of the CRC block we used a Test Bench to test out block and then integrated our CRC block with the rest of the system.
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Conclusions Because we used a CRC that can get any polynomial and didn't use a specific code for a specific polynomial, we needed a general purpose logic design and this design uses a lot of logic cells on the chip. Being a part of a big project gave us all the project definitions that led us in a specific direction but didn't give us a lot of room to maneuver. In this project we learned about VHDL implementations and the usage of the Virtex2 pro chip.
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THE END
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