2. Computer Organization Prepared by:Anh Q. Vu Course:CS-147 Professor:Sin-Min Lee Date:Summer - 2001

3. Computer Organization Contents (Text Book: page 142 – 158) 1.Overview 2.Computer Organization 3.Definitions - Buses 4.Computer Organization Diagram 5.CPU organization Diagram 6.Memory 7.Memory Chip Organization 8.The Instruction Cycle 9.Supporting Diagrams (25 minutes)

4. Computer Organization “Overview” The Intel Microprocessor Evolution MicroprocessorYear introduced# of Transistors 800819723000 808019744500 808519766500 8086197829,000 8088197929,000 802861982130,000 803861985275,000 8048619891.2 million Pentium19923.1 million Pentium Pro19955.5 million Pentium III19999.5 million Pentium 4200042 million

5. Computer Organization

6. A computer is organized into 3 internal parts: 1.CPU 2.Memory 3.I/O (Input/Output)

7. Computer Organization 1.CPU –It is the Central Processing Unit of the computer. –Its function is to execute or process the information stored in memory. –The CPU is connected to memory and I/O through strips of wire called bus.

8. Computer Organization 2.Memory –Memory is the big store house of data located within the main computer outside of the Microprocessor.

9. Computer Organization 3.I/O (Input/Output) –Input devices provide signals to the CPU. »Keyboard, Sensors, Switches, etc. –Output devices take signals from the CPU and perform required actions. »Printers, Monitor, Lights, etc.

10. Computer Organization BUS Bus –Bus is a set of wires that connects the CPU to memory and I/O –It carries information from place to place just as a street bus carries people from place to place. –There are 3 types of bus »Address bus »Data bus »Control bus

11. Computer Organization BUS cont. a)Address bus –Address bus is the set of wires that carries addresses of memory or I/O only. –For a memory or I/O to be recognized by the CPU it must be assigned an address. –The assigned address must be unique; no two devices are allowed to have the same address. –The CPU puts the address on the address bus, and the decoding circuitry finds the device.

12. Computer Organization BUS cont. b)Data bus –Data bus is a set of wires that carries data only. –After finding the device through the address bus, the CPU uses the data bus either to get data or to send data to the device.

13. Computer Organization BUS cont. c)Control bus –Control bus is a set of wires that carries control signals only. –The control buses are used to provide read or write signals to the device to indicate if the CPU is asking or sending information.

14. Computer Organization Diagram CPU RAMROMDiskKeyboard Read/Write Data bus Address bus Control bus Printer/ Monitor

15. CPU Internal Organization Diagram Control Unit ALU Program Counter Instruction Register REGISTERS Register A Register B Register C Etc. Address busControl bus signalsData bus Control signals Data Values Data values (operands) Data values (results)

16. MEMORY

17. Memory Types of Memory Chips 1.ROM Read Only Memory, Not able to write to it. Non Volatile; Retains data when power is turned-off 2.RAM Random Access Memory, able to read and write to it.

18. Memory Types of ROM Chips MROM (Masked Read Only Memory) –Set by manufacturer and cannot be changed –Mostly used on consumer appliances where large quantities are produced. PROM (Programmable Read Only Memory) –Programmable but only once –Programmed by blowing internal fuses –Mostly used for prototypes

19. Memory Types of ROM Chips cont. EPROM (Erasable & Programmable ROM) »Totally erasable by exposing it to ultra violet light for over 20 minutes. »Programmable outside the circuit. EEPROM (Electrically Erasable & Programmable ROM) »Electrically erasable. »Able to erase a portion of the memory. »Can be re programmed while in circuit. »Mostly used for computer BIOS FLASH Memory »Electrically erased, but it erases the entire memory.

20. Memory Types of RAM Chips DRAM (Dynamic Random Access Memory) »Widely used as main computer memory SRAM (Static Random Access Memory) »Faster than DRAM »More expensive than DRAM »Mostly used in Cache memory NVRAM (Non Volatile Random Access Memory) »Does not lose data in memory when turned off. »Contains an internal Lithium battery to retain power

21. Memory Chip Organization The internal organization of ROM and RAM chips are similar. There are two organizations 1.Linear Organization 2.Two-Dimensional organization

22. Memory Chip Organization Linear Organization »It is a simpler form of organization »Used if few number of memory locations are needed

23. Memory Chip Internal Linear Organization of an 8 x 2 ROM chip 3 to 8 Decoder 0101 1 2121 3131 4141 5151 6161 7171 0 1010 2020 3030 4040 5050 6060 7070 A2A2 A1A1 A0A0 E 1 0 2 4 5 3 6 7 CE OE D1D1 D0D0 0000 0011 0102 0113 1004 1015 1106 1117 A2A1A0 Loc#

24. Memory Chip Organization Two-dimensional Organization »Used to manage a large number of memory locations »Allows large memory locations using fewer chips

25. Memory Chip Internal two-dimensional Organization of an 8 x 2 ROM chip 2 to 4 Decoder 0101 2121 4141 6161 1 3131 5151 7171 0 2020 4040 6060 1010 3030 5050 7070 A2A2 A1A1 A0A0 E 1 0 2 3 CE OE D1D1 D0D0 1 to 2 Decoder 0 1 E

26. Instruction Cycle

27. The Instruction Cycle 1.The Fetch cycle Fetch an instruction from memory, then go to the decode cycle 2.The Decode cycle Decode the instruction – determine which instruction has been fetched –go to execute cycle for that instruction. 3.The execute cycle Execute the instruction, then go to fetch cycle and fetch the next instruction.

28. The Instruction Cycle The Fetch cycle »The CPU puts an address of instruction on the address bus. »The memory decodes the address to access the desired memory location. »The CPU allows sufficient time for the memory to decode the address and sends a READ control signal. »The READ signal is a signal on the Control bus which the CPU sends when it’s ready to read data from memory or I/O device. »When the READ signal is asserted, the memory puts the instruction code to be fetched on to the data bus. »The CPU inputs the data and stores it in one of its internal registers. »The fetch cycle is completed.

29. The Instruction Cycle The Decode cycle »The CPU decodes the instruction. »Each instruction may require a different sequence of operations to execute the instruction. »The CPU determines which instruction it is in order to select the correct sequence of operation to perform. »This is done entirely within the CPU, it does not use the system buses.

30. The Instruction Cycle The Execute cycle »The CPU executes the instruction. »The execution may be: 1.Read/write data to/from memory. 2.Read/Write data to/from an I/O device. 3.Perform only operations within the CPU. 4.Perform some combination of the above.

31. Sample Diagrams

32. Fetch, Decode & Execute Cycles 2+3=5 operation

36. The End Thanks!!