1. Transmitter for Quantum Encryption System Supervisor: Yossi Hipsh Performed by: Asaf Holzer Edward Shifman High Speed Digital Systems Laboratory Midterm presentation Spring 2006

2. Project Objectives The transmitter module is part of a complex system, which purpose is to send a digital code, which will later be used as key for encrypting and decrypting information. Our goal is to produce an electrical pulse which is ~0.5ns wide and its magnitude is 4v. The purpose of this pulse is to activate the laser diode.

3. The Overall System Block Diagram Computer (Controller) TransmitterReciever Interfrometers, etc. Computer + Counter Synchronization

4. Original Plan Pulse trigger D.D.LTTL 2 ECL ECL Programmable Delay Chip 1:2 ECL Programmable Delay Chip Long fiber And Gate1:2 Bal_UN Gain P_QuantP_Sync monostable

5. Original Plan – continued… Pulse trigger D.D.LTTL 2 ECL ECL Programmable Delay Chip 1:2 ECL Programmable Delay Chip Long fiber And Gate1:2 Bal_UN Gain RefP_Stab monostable

6. The ECL Programmable Delay Chip SY100EP195V (by Micrel) : Has 10 control bits, so we can delay the pulse by 2-12ns. (Delay range = 2 10 x step_delay = 2 10 x 10ps = 10ns) Conclusion: We can manage without the TTL delay (and the long fiber delay).

7. In order to improve the module’s performance we decided to use ECL technology from the very beginning of the pulse module, so we put the TTL-ECL device at the beginning. We replaced the components so they will operate in 3.3 voltage level. Some more advances

8. Pulse trigger TTL 2 ECL ECL Prog. Delay Chip 1:2And Gate 1:4 Bal_UN Gain monostable ECL Prog. Delay Chip ECL Prog. Delay Chip … … … P_Quant P_Sync Ref Plan #2

9. The Monostable (ECL) Flip Flop S R Q D ECL Prog. Delay Chip 1 ECL Prog. Delay Chip 3 ECL Prog. Delay Chip 2 1:4 (ECL) Q CLK MC100EP31 MC100EP31 Characteristics:

10. The Monostable Timing Diagram Data CLK Reset Q tsts t clk-Q t R-Q Q 400ps130ps Min. Pulse width: 530ps t t t t

11. Final Plan Computer – LabView 1:4 (TTL) Mux TTL-ECL Pulse-Module 1:4 (TTL) sel counter P_QuantP_StabP_Sync stab_ensync_ctrltrig detector ref

12. Inputs & Outputs Voltage Source trig. P_StabP_Quant (0.5 nsec) P_SyncRef (1) Ref (2) stab_ensync_ctrl counter

13. Final Plan – Pulse Module monostable And Gate 1:2 Bal_UN Gain Plan B 3ns0.5ns 10ns ref

14. Flip Flop S R Q D ECL Prog. Delay Chip 2 ECL Prog. Delay Chip 1 1:4 (ECL) Q CLK Final Plan – Pulse Module Flip Flop S R Q D ECL Prog. Delay Chip 3 ECL Prog. Delay Chip 5 ECL Prog. Delay Chip 4 1:4 (ECL) Q CLK 3ns 0.5ns And Gate 0.5ns

15. Final Plan – Timing Delays Time Table: Delay 1: 6.0ns Delay 2: 3.0ns Delay 3: 3.0ns 3.0ns Delay 4: 3.84ns 3.5ns Delay 5: 3.5ns 6.35ns Plan APlan B

16. The Bal-UN IN OUT 68Ω 140Ω 150Ω 1nF 100nF + -

17. Component List ComponentDescriptionManufacturerQuantity NB3L553-D1:4 TTLON Semi2 NLASB3157-DF (*)Multiplexer TTLON Semi2 MC100EPT20-DTTTL-PECLON Semi3 NB6N14S-MN (*)1:4 PECLON Semi6 MC100EP195-FAECL Prog. DelayON Semi15 MC100EP31 -DT (*)Flip FlopON Semi6 MC100EP05-DTN/AND GateON Semi3 MC100EP11-DT1:2 PECLON Semi3 (Self-Built)Bal-UN(Self-Built)6 ZPUL-30PAmplifierMini Circuits6 (*) To be approved by the project supervisor

18. The Transmitter Block Diagram P_Quant FPGA Spartan III PulseModule 1 P_Stab PulseModule 2 P_Sync PulseModule 3 Bus1Bus2

19. Achieved so far: Finished final design including pulse module with improvements (discussed before) Components have been chosen (some still waiting to be approved by the supervisor). Currently working on Orcad scheme.

20. Yet to do Approving new design by supervisor, including components. Finishing Orcad scheme. Ordering components. Wiring-up the circuit. Writing VHDL for the FPGA. Testing the wired-up circuit.